From patchwork Tue Oct 18 07:16:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niranjana Vishwanathapura X-Patchwork-Id: 13010049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61A00C433FE for ; Tue, 18 Oct 2022 07:17:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36FE710E192; Tue, 18 Oct 2022 07:16:46 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 134B010E1E8; Tue, 18 Oct 2022 07:16:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666077398; x=1697613398; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s2SytYlZ4XW8IHH4S3RWx/PSLW3YXP5X/WijwHLKFdA=; b=Q4ofaIvW4rM+0YxsqTkL8y8JOq4S8Hx36FWnQIctzD6pDH/geIXrHAte jfytTbOBn+ns5H9p2CK6kL2xwBPO/+hy0ikmFCknm2VniP3a9nyTanH+T caqBCQVWpkvy53Mc92hRPyN7BO0E78iKiS8xJXY7eJ3N+o0XzLSMInSPY hE3tjakG/r1BlE8N2R5VjUoVQnwfDVwKQjREslZLDd0r6p3eYjFsva3J7 0PejktvZS4PT+e56LCVhhfPx6kbQpsWhdI2d0TUd40jKL06i1PjTqgRyf K8ubEQc4+9QKskORdLx6v27HFOCHOaBzZICu1MqiPAzuKlKJQ2PrtKjsw Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="370221311" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="370221311" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 00:16:37 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661783454" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661783454" Received: from nvishwa1-desk.sc.intel.com ([172.25.29.76]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 00:16:37 -0700 From: Niranjana Vishwanathapura To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v4 02/17] drm/i915/vm_bind: Add __i915_sw_fence_await_reservation() Date: Tue, 18 Oct 2022 00:16:15 -0700 Message-Id: <20221018071630.3831-3-niranjana.vishwanathapura@intel.com> X-Mailer: git-send-email 2.21.0.rc0.32.g243a4c7e27 In-Reply-To: <20221018071630.3831-1-niranjana.vishwanathapura@intel.com> References: <20221018071630.3831-1-niranjana.vishwanathapura@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.brost@intel.com, paulo.r.zanoni@intel.com, tvrtko.ursulin@intel.com, jani.nikula@intel.com, lionel.g.landwerlin@intel.com, thomas.hellstrom@intel.com, matthew.auld@intel.com, jason@jlekstrand.net, andi.shyti@linux.intel.com, daniel.vetter@intel.com, christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add function __i915_sw_fence_await_reservation() for asynchronous wait on a dma-resv object with specified dma_resv_usage. This is required for async vma unbind with vm_bind. Reviewed-by: Matthew Auld Signed-off-by: Niranjana Vishwanathapura --- drivers/gpu/drm/i915/i915_sw_fence.c | 28 +++++++++++++++++++++------- drivers/gpu/drm/i915/i915_sw_fence.h | 23 +++++++++++++++++------ 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_sw_fence.c b/drivers/gpu/drm/i915/i915_sw_fence.c index cc2a8821d22a..ae06d35db056 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.c +++ b/drivers/gpu/drm/i915/i915_sw_fence.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "i915_sw_fence.h" #include "i915_selftest.h" @@ -569,11 +568,26 @@ int __i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, return ret; } -int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, - struct dma_resv *resv, - bool write, - unsigned long timeout, - gfp_t gfp) +/** + * __i915_sw_fence_await_reservation() - Setup a fence to wait on a dma-resv + * object with specified usage. + * @fence: the fence that needs to wait + * @resv: dma-resv object + * @usage: dma_resv_usage (See enum dma_resv_usage) + * @timeout: how long to wait in jiffies + * @gfp: allocation mode + * + * Setup the @fence to asynchronously wait on dma-resv object @resv for + * @usage to complete before signaling. + * + * Returns 0 if there is nothing to wait on, -ve error code upon error + * and >0 upon successfully setting up the wait. + */ +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + enum dma_resv_usage usage, + unsigned long timeout, + gfp_t gfp) { struct dma_resv_iter cursor; struct dma_fence *f; @@ -582,7 +596,7 @@ int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, debug_fence_assert(fence); might_sleep_if(gfpflags_allow_blocking(gfp)); - dma_resv_iter_begin(&cursor, resv, dma_resv_usage_rw(write)); + dma_resv_iter_begin(&cursor, resv, usage); dma_resv_for_each_fence_unlocked(&cursor, f) { pending = i915_sw_fence_await_dma_fence(fence, f, timeout, gfp); diff --git a/drivers/gpu/drm/i915/i915_sw_fence.h b/drivers/gpu/drm/i915/i915_sw_fence.h index f752bfc7c6e1..9c4859dc4c0d 100644 --- a/drivers/gpu/drm/i915/i915_sw_fence.h +++ b/drivers/gpu/drm/i915/i915_sw_fence.h @@ -10,13 +10,13 @@ #define _I915_SW_FENCE_H_ #include +#include #include #include #include /* for NOTIFY_DONE */ #include struct completion; -struct dma_resv; struct i915_sw_fence; enum i915_sw_fence_notify { @@ -89,11 +89,22 @@ int i915_sw_fence_await_dma_fence(struct i915_sw_fence *fence, unsigned long timeout, gfp_t gfp); -int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, - struct dma_resv *resv, - bool write, - unsigned long timeout, - gfp_t gfp); +int __i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + enum dma_resv_usage usage, + unsigned long timeout, + gfp_t gfp); + +static inline int i915_sw_fence_await_reservation(struct i915_sw_fence *fence, + struct dma_resv *resv, + bool write, + unsigned long timeout, + gfp_t gfp) +{ + return __i915_sw_fence_await_reservation(fence, resv, + dma_resv_usage_rw(write), + timeout, gfp); +} bool i915_sw_fence_await(struct i915_sw_fence *fence); void i915_sw_fence_complete(struct i915_sw_fence *fence);