| Message ID | 20221103091243.96036-3-allen.chen@ite.com.tw (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | *** IT6505 driver read dt properties *** | expand |
Hi all, Friendly ping on this patch. Regards, Pin-yen On Thu, Nov 3, 2022 at 5:13 PM allen <allen.chen@ite.com.tw> wrote: > > From: allen chen <allen.chen@ite.com.tw> > > Add driver to read data-lanes and link-frequencies from dt property to > restrict output bandwidth. > > Signed-off-by: Allen chen <allen.chen@ite.com.tw> > Signed-off-by: Pin-yen Lin <treapking@chromium.org> > --- > drivers/gpu/drm/bridge/ite-it6505.c | 80 +++++++++++++++++++++++++++-- > 1 file changed, 77 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c > index a4302492cf8df..ed4536cde3140 100644 > --- a/drivers/gpu/drm/bridge/ite-it6505.c > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > @@ -437,6 +437,8 @@ struct it6505 { > bool powered; > bool hpd_state; > u32 afe_setting; > + u32 max_dpi_pixel_clock; > + u32 max_lane_count; > enum hdcp_state hdcp_status; > struct delayed_work hdcp_work; > struct work_struct hdcp_wait_ksv_list; > @@ -1476,7 +1478,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505) > it6505->lane_count = link->num_lanes; > DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", > it6505->lane_count); > - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); > + it6505->lane_count = min_t(int, it6505->lane_count, > + it6505->max_lane_count); > > it6505->branch_device = drm_dp_is_branch(it6505->dpcd); > DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", > @@ -2912,7 +2915,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, > if (mode->flags & DRM_MODE_FLAG_INTERLACE) > return MODE_NO_INTERLACE; > > - if (mode->clock > DPI_PIXEL_CLK_MAX) > + if (mode->clock > it6505->max_dpi_pixel_clock) > return MODE_CLOCK_HIGH; > > it6505->video_info.clock = mode->clock; > @@ -3099,10 +3102,32 @@ static int it6505_init_pdata(struct it6505 *it6505) > return 0; > } > > +static int it6505_get_data_lanes_count(const struct device_node *endpoint, > + const unsigned int min, > + const unsigned int max) > +{ > + int ret; > + > + ret = of_property_count_u32_elems(endpoint, "data-lanes"); > + if (ret < 0) > + return ret; > + > + if (ret < min || ret > max) > + return -EINVAL; > + > + return ret; > +} > + > static void it6505_parse_dt(struct it6505 *it6505) > { > struct device *dev = &it6505->client->dev; > + struct device_node *np = dev->of_node, *ep = NULL; > + int len; > + u64 link_frequencies; > + u32 data_lanes[4]; > u32 *afe_setting = &it6505->afe_setting; > + u32 *max_lane_count = &it6505->max_lane_count; > + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock; > > it6505->lane_swap_disabled = > device_property_read_bool(dev, "no-laneswap"); > @@ -3118,7 +3143,56 @@ static void it6505_parse_dt(struct it6505 *it6505) > } else { > *afe_setting = 0; > } > - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); > + > + ep = of_graph_get_endpoint_by_regs(np, 1, 0); > + of_node_put(ep); > + > + if (ep) { > + len = it6505_get_data_lanes_count(ep, 1, 4); > + > + if (len > 0 && len != 3) { > + of_property_read_u32_array(ep, "data-lanes", > + data_lanes, len); > + *max_lane_count = len; > + } else { > + *max_lane_count = MAX_LANE_COUNT; > + dev_err(dev, "error data-lanes, use default"); > + } > + } else { > + *max_lane_count = MAX_LANE_COUNT; > + dev_err(dev, "error endpoint, use default"); > + } > + > + ep = of_graph_get_endpoint_by_regs(np, 0, 0); > + of_node_put(ep); > + > + if (ep) { > + len = of_property_read_variable_u64_array(ep, > + "link-frequencies", > + &link_frequencies, 0, > + 1); > + if (len >= 0) { > + do_div(link_frequencies, 1000); > + if (link_frequencies > 297000) { > + dev_err(dev, > + "max pixel clock error, use default"); > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > + } else { > + *max_dpi_pixel_clock = link_frequencies; > + } > + } else { > + dev_err(dev, "error link frequencies, use default"); > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > + } > + } else { > + dev_err(dev, "error endpoint, use default"); > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > + } > + > + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", > + it6505->afe_setting, it6505->max_lane_count); > + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", > + it6505->max_dpi_pixel_clock); > } > > static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf, > -- > 2.25.1 >
Friendly ping. Pin-yen Pin-yen On Mon, Nov 21, 2022 at 1:39 PM Pin-yen Lin <treapking@chromium.org> wrote: > > Hi all, > Friendly ping on this patch. > > Regards, > Pin-yen > > On Thu, Nov 3, 2022 at 5:13 PM allen <allen.chen@ite.com.tw> wrote: > > > > From: allen chen <allen.chen@ite.com.tw> > > > > Add driver to read data-lanes and link-frequencies from dt property to > > restrict output bandwidth. > > > > Signed-off-by: Allen chen <allen.chen@ite.com.tw> > > Signed-off-by: Pin-yen Lin <treapking@chromium.org> > > --- > > drivers/gpu/drm/bridge/ite-it6505.c | 80 +++++++++++++++++++++++++++-- > > 1 file changed, 77 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c > > index a4302492cf8df..ed4536cde3140 100644 > > --- a/drivers/gpu/drm/bridge/ite-it6505.c > > +++ b/drivers/gpu/drm/bridge/ite-it6505.c > > @@ -437,6 +437,8 @@ struct it6505 { > > bool powered; > > bool hpd_state; > > u32 afe_setting; > > + u32 max_dpi_pixel_clock; > > + u32 max_lane_count; > > enum hdcp_state hdcp_status; > > struct delayed_work hdcp_work; > > struct work_struct hdcp_wait_ksv_list; > > @@ -1476,7 +1478,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505) > > it6505->lane_count = link->num_lanes; > > DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", > > it6505->lane_count); > > - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); > > + it6505->lane_count = min_t(int, it6505->lane_count, > > + it6505->max_lane_count); > > > > it6505->branch_device = drm_dp_is_branch(it6505->dpcd); > > DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", > > @@ -2912,7 +2915,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, > > if (mode->flags & DRM_MODE_FLAG_INTERLACE) > > return MODE_NO_INTERLACE; > > > > - if (mode->clock > DPI_PIXEL_CLK_MAX) > > + if (mode->clock > it6505->max_dpi_pixel_clock) > > return MODE_CLOCK_HIGH; > > > > it6505->video_info.clock = mode->clock; > > @@ -3099,10 +3102,32 @@ static int it6505_init_pdata(struct it6505 *it6505) > > return 0; > > } > > > > +static int it6505_get_data_lanes_count(const struct device_node *endpoint, > > + const unsigned int min, > > + const unsigned int max) > > +{ > > + int ret; > > + > > + ret = of_property_count_u32_elems(endpoint, "data-lanes"); > > + if (ret < 0) > > + return ret; > > + > > + if (ret < min || ret > max) > > + return -EINVAL; > > + > > + return ret; > > +} > > + > > static void it6505_parse_dt(struct it6505 *it6505) > > { > > struct device *dev = &it6505->client->dev; > > + struct device_node *np = dev->of_node, *ep = NULL; > > + int len; > > + u64 link_frequencies; > > + u32 data_lanes[4]; > > u32 *afe_setting = &it6505->afe_setting; > > + u32 *max_lane_count = &it6505->max_lane_count; > > + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock; > > > > it6505->lane_swap_disabled = > > device_property_read_bool(dev, "no-laneswap"); > > @@ -3118,7 +3143,56 @@ static void it6505_parse_dt(struct it6505 *it6505) > > } else { > > *afe_setting = 0; > > } > > - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); > > + > > + ep = of_graph_get_endpoint_by_regs(np, 1, 0); > > + of_node_put(ep); > > + > > + if (ep) { > > + len = it6505_get_data_lanes_count(ep, 1, 4); > > + > > + if (len > 0 && len != 3) { > > + of_property_read_u32_array(ep, "data-lanes", > > + data_lanes, len); > > + *max_lane_count = len; > > + } else { > > + *max_lane_count = MAX_LANE_COUNT; > > + dev_err(dev, "error data-lanes, use default"); > > + } > > + } else { > > + *max_lane_count = MAX_LANE_COUNT; > > + dev_err(dev, "error endpoint, use default"); > > + } > > + > > + ep = of_graph_get_endpoint_by_regs(np, 0, 0); > > + of_node_put(ep); > > + > > + if (ep) { > > + len = of_property_read_variable_u64_array(ep, > > + "link-frequencies", > > + &link_frequencies, 0, > > + 1); > > + if (len >= 0) { > > + do_div(link_frequencies, 1000); > > + if (link_frequencies > 297000) { > > + dev_err(dev, > > + "max pixel clock error, use default"); > > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > > + } else { > > + *max_dpi_pixel_clock = link_frequencies; > > + } > > + } else { > > + dev_err(dev, "error link frequencies, use default"); > > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > > + } > > + } else { > > + dev_err(dev, "error endpoint, use default"); > > + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; > > + } > > + > > + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", > > + it6505->afe_setting, it6505->max_lane_count); > > + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", > > + it6505->max_dpi_pixel_clock); > > } > > > > static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf, > > -- > > 2.25.1 > >
diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index a4302492cf8df..ed4536cde3140 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -437,6 +437,8 @@ struct it6505 { bool powered; bool hpd_state; u32 afe_setting; + u32 max_dpi_pixel_clock; + u32 max_lane_count; enum hdcp_state hdcp_status; struct delayed_work hdcp_work; struct work_struct hdcp_wait_ksv_list; @@ -1476,7 +1478,8 @@ static void it6505_parse_link_capabilities(struct it6505 *it6505) it6505->lane_count = link->num_lanes; DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training", it6505->lane_count); - it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); + it6505->lane_count = min_t(int, it6505->lane_count, + it6505->max_lane_count); it6505->branch_device = drm_dp_is_branch(it6505->dpcd); DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device", @@ -2912,7 +2915,7 @@ it6505_bridge_mode_valid(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_INTERLACE) return MODE_NO_INTERLACE; - if (mode->clock > DPI_PIXEL_CLK_MAX) + if (mode->clock > it6505->max_dpi_pixel_clock) return MODE_CLOCK_HIGH; it6505->video_info.clock = mode->clock; @@ -3099,10 +3102,32 @@ static int it6505_init_pdata(struct it6505 *it6505) return 0; } +static int it6505_get_data_lanes_count(const struct device_node *endpoint, + const unsigned int min, + const unsigned int max) +{ + int ret; + + ret = of_property_count_u32_elems(endpoint, "data-lanes"); + if (ret < 0) + return ret; + + if (ret < min || ret > max) + return -EINVAL; + + return ret; +} + static void it6505_parse_dt(struct it6505 *it6505) { struct device *dev = &it6505->client->dev; + struct device_node *np = dev->of_node, *ep = NULL; + int len; + u64 link_frequencies; + u32 data_lanes[4]; u32 *afe_setting = &it6505->afe_setting; + u32 *max_lane_count = &it6505->max_lane_count; + u32 *max_dpi_pixel_clock = &it6505->max_dpi_pixel_clock; it6505->lane_swap_disabled = device_property_read_bool(dev, "no-laneswap"); @@ -3118,7 +3143,56 @@ static void it6505_parse_dt(struct it6505 *it6505) } else { *afe_setting = 0; } - DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting); + + ep = of_graph_get_endpoint_by_regs(np, 1, 0); + of_node_put(ep); + + if (ep) { + len = it6505_get_data_lanes_count(ep, 1, 4); + + if (len > 0 && len != 3) { + of_property_read_u32_array(ep, "data-lanes", + data_lanes, len); + *max_lane_count = len; + } else { + *max_lane_count = MAX_LANE_COUNT; + dev_err(dev, "error data-lanes, use default"); + } + } else { + *max_lane_count = MAX_LANE_COUNT; + dev_err(dev, "error endpoint, use default"); + } + + ep = of_graph_get_endpoint_by_regs(np, 0, 0); + of_node_put(ep); + + if (ep) { + len = of_property_read_variable_u64_array(ep, + "link-frequencies", + &link_frequencies, 0, + 1); + if (len >= 0) { + do_div(link_frequencies, 1000); + if (link_frequencies > 297000) { + dev_err(dev, + "max pixel clock error, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } else { + *max_dpi_pixel_clock = link_frequencies; + } + } else { + dev_err(dev, "error link frequencies, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + } else { + dev_err(dev, "error endpoint, use default"); + *max_dpi_pixel_clock = DPI_PIXEL_CLK_MAX; + } + + DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %u, max_lane_count: %u", + it6505->afe_setting, it6505->max_lane_count); + DRM_DEV_DEBUG_DRIVER(dev, "using max_dpi_pixel_clock: %u kHz", + it6505->max_dpi_pixel_clock); } static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,