| Message ID | 20221119173019.15643-6-a-bhatia1@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSS support for AM625 SoC | expand |
On 19/11/2022 19:30, Aradhya Bhatia wrote: > The AM625 DSS IP contains 2 OLDI TXes which can work together to enable 2 > cloned displays of or even a single dual-link display with higher > resolutions like WUXGA (1920x1200@60fps) with a reduced OLDI clock > frequency. > > Configure the necessary register to enable and disable the OLDI TXes > with required modes configurations. > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > drivers/gpu/drm/tidss/tidss_dispc.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c > index f26129fb1d8f..cf43de6216a5 100644 > --- a/drivers/gpu/drm/tidss/tidss_dispc.c > +++ b/drivers/gpu/drm/tidss/tidss_dispc.c > @@ -1012,8 +1012,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, > int count = 0; > > /* > - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC > - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. > + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are > + * always set to 0. > */ > > if (fmt->data_width == 24) > @@ -1030,6 +1030,26 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, > > oldi_cfg |= BIT(0); /* ENABLE */ > > + switch (dispc->oldi_mode) { > + case OLDI_SINGLE_LINK_SINGLE_MODE: > + /* All configuration is done for this mode. */ > + break; > + > + case OLDI_SINGLE_LINK_CLONE_MODE: > + oldi_cfg |= BIT(5); /* CLONE MODE */ > + break; > + > + case OLDI_DUAL_LINK_MODE: > + oldi_cfg |= BIT(11); /* DUALMODESYNC */ > + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ > + break; > + > + default: > + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", > + __func__); > + return; > + } > + > dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); > > while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c index f26129fb1d8f..cf43de6216a5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1012,8 +1012,8 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, int count = 0; /* - * For the moment DUALMODESYNC, MASTERSLAVE, MODE, and SRC - * bits of DISPC_VP_DSS_OLDI_CFG are set statically to 0. + * For the moment MASTERSLAVE, and SRC bits of DISPC_VP_DSS_OLDI_CFG are + * always set to 0. */ if (fmt->data_width == 24) @@ -1030,6 +1030,26 @@ static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, oldi_cfg |= BIT(0); /* ENABLE */ + switch (dispc->oldi_mode) { + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* All configuration is done for this mode. */ + break; + + case OLDI_SINGLE_LINK_CLONE_MODE: + oldi_cfg |= BIT(5); /* CLONE MODE */ + break; + + case OLDI_DUAL_LINK_MODE: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ + break; + + default: + dev_warn(dispc->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
The AM625 DSS IP contains 2 OLDI TXes which can work together to enable 2 cloned displays of or even a single dual-link display with higher resolutions like WUXGA (1920x1200@60fps) with a reduced OLDI clock frequency. Configure the necessary register to enable and disable the OLDI TXes with required modes configurations. Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> --- drivers/gpu/drm/tidss/tidss_dispc.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)