| Message ID | 20221120133744.24808-2-a39.skl@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add SM6115 MDSS/DPU support | expand |
On Sun, Nov 20, 2022 at 02:37:36PM +0100, Adam Skladowski wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM6115 platform. > Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. > Lack of dsi phy supply in example is intended > due to fact on qcm2290, sm6115 and sm6125 > this phy is supplied via power domain, not regulator. The subject needs 'sm6115' somewhere. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- > .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ > .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ > 2 files changed, 274 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > new file mode 100644 > index 000000000000..cc77675ec4f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for SM6115 target > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set Drop 'Address offset and size for'. s/mdp/MDP/ ? s/vbif/VBIF/ ? > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display AXI clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock from dispcc > + - description: Display lut clock from dispcc > + - description: Display rotator clock from dispcc > + - description: Display vsync clock from dispcc Source of the clock is outside the scope of the binding. > + > + clock-names: > + items: > + - const: bus > + - const: iface > + - const: core > + - const: lut > + - const: rot > + - const: vsync > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > new file mode 100644 > index 000000000000..af721aa05b22 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > @@ -0,0 +1,187 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM6115 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS > + are mentioned for SM6115 target. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AXI clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + > + iommus: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm6115-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-ctrl-6g-qcm2290 > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-14nm-2290 > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/clock/qcom,rpmcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + mdss@5e00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,sm6115-mdss"; > + reg = <0x05e00000 0x1000>; > + reg-names = "mdss"; > + power-domains = <&dispcc MDSS_GDSC>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "core"; > + > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x420 0x2>, > + <&apps_smmu 0x421 0x0>; > + ranges; > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi@5e94000 { > + compatible = "qcom,dsi-ctrl-6g-qcm2290"; > + reg = <0x05e94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: phy@5e94400 { > + compatible = "qcom,dsi-phy-14nm-2290"; > + reg = <0x05e94400 0x100>, > + <0x05e94500 0x300>, > + <0x05e94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "iface", "ref"; > + }; > + }; > +... > -- > 2.25.1 > >
On 20/11/2022 15:37, Adam Skladowski wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM6115 platform. > Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. > Lack of dsi phy supply in example is intended > due to fact on qcm2290, sm6115 and sm6125 > this phy is supplied via power domain, not regulator. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- > .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ > .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ > 2 files changed, 274 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > new file mode 100644 > index 000000000000..cc77675ec4f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for SM6115 target > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display AXI clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock from dispcc > + - description: Display lut clock from dispcc > + - description: Display rotator clock from dispcc > + - description: Display vsync clock from dispcc > + > + clock-names: > + items: > + - const: bus > + - const: iface > + - const: core > + - const: lut > + - const: rot > + - const: vsync Please add: required: - compatible - reg - reg-names - clocks - clock-names Per Krzysztof's request these requirements are migrating from dpu-common to individual dpu schemas > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > new file mode 100644 > index 000000000000..af721aa05b22 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > @@ -0,0 +1,187 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM6115 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS > + are mentioned for SM6115 target. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AXI clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core > + > + iommus: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm6115-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-ctrl-6g-qcm2290 > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-14nm-2290 required: compatible The same story > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/clock/qcom,rpmcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + mdss@5e00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,sm6115-mdss"; > + reg = <0x05e00000 0x1000>; > + reg-names = "mdss"; > + power-domains = <&dispcc MDSS_GDSC>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "core"; > + > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x420 0x2>, > + <&apps_smmu 0x421 0x0>; > + ranges; > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi@5e94000 { > + compatible = "qcom,dsi-ctrl-6g-qcm2290"; > + reg = <0x05e94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + phys = <&dsi0_phy>; > + phy-names = "dsi"; phy-names are being phased out, please drop this line. > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: phy@5e94400 { > + compatible = "qcom,dsi-phy-14nm-2290"; > + reg = <0x05e94400 0x100>, > + <0x05e94500 0x300>, > + <0x05e94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "iface", "ref"; > + }; > + }; > +...
On 20/11/2022 15:37, Adam Skladowski wrote: > Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm > SM6115 platform. > Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. > Lack of dsi phy supply in example is intended > due to fact on qcm2290, sm6115 and sm6125 > this phy is supplied via power domain, not regulator. > > Signed-off-by: Adam Skladowski <a39.skl@gmail.com> > --- > .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ > .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ > 2 files changed, 274 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > new file mode 100644 > index 000000000000..cc77675ec4f6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Display DPU dt properties for SM6115 target > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +$ref: /schemas/display/msm/dpu-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-dpu > + > + reg: > + items: > + - description: Address offset and size for mdp register set > + - description: Address offset and size for vbif register set > + > + reg-names: > + items: > + - const: mdp > + - const: vbif > + > + clocks: > + items: > + - description: Display AXI clock from gcc > + - description: Display AHB clock from dispcc > + - description: Display core clock from dispcc > + - description: Display lut clock from dispcc > + - description: Display rotator clock from dispcc > + - description: Display vsync clock from dispcc > + > + clock-names: > + items: > + - const: bus > + - const: iface > + - const: core > + - const: lut > + - const: rot > + - const: vsync > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > +... > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > new file mode 100644 > index 000000000000..af721aa05b22 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml > @@ -0,0 +1,187 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SM6115 Display MDSS > + > +maintainers: > + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > + > +description: > + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates > + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS > + are mentioned for SM6115 target. > + > +$ref: /schemas/display/msm/mdss-common.yaml# > + > +properties: > + compatible: > + items: > + - const: qcom,sm6115-mdss > + > + clocks: > + items: > + - description: Display AHB clock from gcc > + - description: Display AXI clock > + - description: Display core clock > + > + clock-names: > + items: > + - const: iface > + - const: bus > + - const: core I think you can drop clock-names from the MDSS node. > + > + iommus: > + maxItems: 2 > + > +patternProperties: > + "^display-controller@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,sm6115-dpu > + > + "^dsi@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-ctrl-6g-qcm2290 > + > + "^phy@[0-9a-f]+$": > + type: object > + properties: > + compatible: > + const: qcom,dsi-phy-14nm-2290 > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> > + #include <dt-bindings/clock/qcom,gcc-sm6115.h> > + #include <dt-bindings/clock/qcom,rpmcc.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + mdss@5e00000 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "qcom,sm6115-mdss"; > + reg = <0x05e00000 0x1000>; > + reg-names = "mdss"; > + power-domains = <&dispcc MDSS_GDSC>; > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + clock-names = "iface", "bus", "core"; > + > + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x420 0x2>, > + <&apps_smmu 0x421 0x0>; > + ranges; > + > + display-controller@5e01000 { > + compatible = "qcom,sm6115-dpu"; > + reg = <0x05e01000 0x8f000>, > + <0x05eb0000 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_ROT_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&dsi0_in>; > + }; > + }; > + }; > + }; > + > + dsi@5e94000 { > + compatible = "qcom,dsi-ctrl-6g-qcm2290"; > + reg = <0x05e94000 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; > + > + operating-points-v2 = <&dsi_opp_table>; > + power-domains = <&rpmpd SM6115_VDDCX>; > + phys = <&dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi0_phy: phy@5e94400 { > + compatible = "qcom,dsi-phy-14nm-2290"; > + reg = <0x05e94400 0x100>, > + <0x05e94500 0x300>, > + <0x05e94800 0x188>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "iface", "ref"; > + }; > + }; > +...
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml new file mode 100644 index 000000000000..cc77675ec4f6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM6115 target + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AXI clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock from dispcc + - description: Display lut clock from dispcc + - description: Display rotator clock from dispcc + - description: Display vsync clock from dispcc + + clock-names: + items: + - const: bus + - const: iface + - const: core + - const: lut + - const: rot + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml new file mode 100644 index 000000000000..af721aa05b22 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS + are mentioned for SM6115 target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6115-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6115-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-ctrl-6g-qcm2290 + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-14nm-2290 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm6115-dispcc.h> + #include <dt-bindings/clock/qcom,gcc-sm6115.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + mdss@5e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc MDSS_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +...
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform. Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended due to fact on qcm2290, sm6115 and sm6125 this phy is supplied via power domain, not regulator. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> --- .../bindings/display/msm/qcom,sm6115-dpu.yaml | 87 ++++++++ .../display/msm/qcom,sm6115-mdss.yaml | 187 ++++++++++++++++++ 2 files changed, 274 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml