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[83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:07 -0800 (PST) From: Adam Skladowski To: Subject: [PATCH 07/12] arm64: dts: qcom: sm6115: Add dispcc node Date: Tue, 29 Nov 2022 21:46:11 +0100 Message-Id: <20221129204616.47006-8-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Rafael J. Wysocki" , Amit Kucheria , dri-devel@lists.freedesktop.org, Krzysztof Kozlowski , phone-devel@vger.kernel.org, Daniel Lezcano , Andy Gross , Zhang Rui , devicetree@vger.kernel.org, Thara Gopinath , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, Adam Skladowski , Abhinav Kumar , Rob Herring , ~postmarketos/upstreaming@lists.sr.ht, Sean Paul , Loic Poulain , Bjorn Andersson , linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add display clock controller to allow controlling display related clocks. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 6d14bbcda9d3..ea0e0b3c5d84 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -717,6 +718,19 @@ usb_1_dwc3: usb@4e00000 { }; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,sm6115-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>;