From patchwork Tue Nov 29 20:46:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 13059190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33D68C4332F for ; Tue, 29 Nov 2022 20:47:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1171310E3D9; Tue, 29 Nov 2022 20:47:27 +0000 (UTC) Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59DD610E388; Tue, 29 Nov 2022 20:47:10 +0000 (UTC) Received: by mail-lj1-x234.google.com with SMTP id z24so18652088ljn.4; Tue, 29 Nov 2022 12:47:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mxN9saAhaHyj6ZPoVgv7tMWvA+bJrGztagX7f0iYRp8=; b=EKOfkRku6K7RAUf9XDjX/bzJEeMBGnJr+YgZZCT2E089whrohH/xepfl97H3rygCBq SSxX2sTPQciwjd83RIArZYSAd1HyGTI5mZ9alPUpHjgIMkgf4GcAr75DnwRyGvxPALWQ m9K2G0MWUvNQ1WhZFDiw2zX8J3pM8cFZlgoVtSOYaV8FMdOUk7VJFpiyy+wnyL8uEyIR QUq2Sw5eBNI1OI6iuLoZZH/MRJTDvWH1rrSfLeDb7tuAV2QNNJoSD4r5KhjHjborxb6e gaALpF8Xne2RnO9LG3uEnssIForFJoZcVATf6Rf3E4ZUDsGq3qZljtU6y2F49Tk1TPMh lzpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxN9saAhaHyj6ZPoVgv7tMWvA+bJrGztagX7f0iYRp8=; b=YiYuaT2UfrCwv+FOV+xwYqBw2jFXzOchLsHVy+1cdzCUMEeno0+YfbbX6lakvlk11k jZfAgDpliLhZjgcrR3RWdDjm4PumbKtNVcMnowTPemSFXt4Za3kuagwMLwf6Ge0XGvpM rWYEsGyjd+sNAiaLPMvGAzRzppMJCdosc2RMFNEzCgPvyzX3IaYIJmeEV+zCDpNSF8XT 9AKq8AgH2Lo31DVL42KFNwOznB9uZQb/gm8UXGTKxWX1w37mNcgtVSxyskk5Z+cT3U5s fFx64xjSwwym1QJVsMr+ty3/iocTu4m6noiV7FYLJ01olEKiB4EFD+uWsZKh/UJBEQ5O yQYw== X-Gm-Message-State: ANoB5pnCvaxvF6wLlXHqGITuQng81KBReajtUbvwX/zy7Ob98N1oWZnd HmGDx8ZJVwdGP1Z1jKiavl0= X-Google-Smtp-Source: AA0mqf4Nem329kgRkNkWL4kY5oPzJemV9ZG8Z58VHEC6R2xw4BnxpGydh7FQmoDxjQByrNViKPSraA== X-Received: by 2002:a2e:2c0e:0:b0:279:8d29:193c with SMTP id s14-20020a2e2c0e000000b002798d29193cmr8569437ljs.167.1669754829867; Tue, 29 Nov 2022 12:47:09 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:09 -0800 (PST) From: Adam Skladowski To: Subject: [PATCH 08/12] arm64: dts: qcom: sm6115: Add mdss/dpu node Date: Tue, 29 Nov 2022 21:46:12 +0100 Message-Id: <20221129204616.47006-9-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Rafael J. Wysocki" , Amit Kucheria , dri-devel@lists.freedesktop.org, Krzysztof Kozlowski , phone-devel@vger.kernel.org, Daniel Lezcano , Andy Gross , Zhang Rui , devicetree@vger.kernel.org, Thara Gopinath , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, Adam Skladowski , Abhinav Kumar , Rob Herring , ~postmarketos/upstreaming@lists.sr.ht, Sean Paul , Loic Poulain , Bjorn Andersson , linux-kernel@vger.kernel.org, Konrad Dybcio , Dmitry Baryshkov , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add mdss and dpu node to enable display support on SM6115. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 183 +++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index ea0e0b3c5d84..b459f1746a7f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -718,6 +718,189 @@ usb_1_dwc3: usb@4e00000 { }; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdp: display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "core", + "lut", + "rot", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,sm6115-dispcc"; reg = <0x05f00000 0x20000>;