| Message ID | 20221130170723.2460014-1-wayne.boyer@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [linux-gfx] drm/i915/pvc: Implement recommended caching policy | expand |
On Wed, Nov 30, 2022 at 09:07:23AM -0800, Wayne Boyer wrote: > As per the performance tuning guide, set the HOSTCACHEEN bit to > implement the recommended caching policy on PVC. > > Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 784152548472..f96570995cfc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -973,6 +973,7 @@ > #define GEN7_L3AGDIS (1 << 19) > > #define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c) > +#define XEHPC_HOSTCACHEEN REG_BIT(1) > #define XEHPC_OVRLSCCC REG_BIT(0) > > #define GEN7_L3CNTLREG2 _MMIO(0xb020) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 1b0e40e68a9d..35e3f43e8b06 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2903,6 +2903,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915, > if (IS_PONTEVECCHIO(i915)) { > wa_write(wal, XEHPC_L3SCRUB, > SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); > + wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); > } > > if (IS_DG2(i915)) { > -- > 2.37.3 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 784152548472..f96570995cfc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -973,6 +973,7 @@ #define GEN7_L3AGDIS (1 << 19) #define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c) +#define XEHPC_HOSTCACHEEN REG_BIT(1) #define XEHPC_OVRLSCCC REG_BIT(0) #define GEN7_L3CNTLREG2 _MMIO(0xb020) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1b0e40e68a9d..35e3f43e8b06 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2903,6 +2903,7 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915, if (IS_PONTEVECCHIO(i915)) { wa_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); + wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); } if (IS_DG2(i915)) {
As per the performance tuning guide, set the HOSTCACHEEN bit to implement the recommended caching policy on PVC. Signed-off-by: Wayne Boyer <wayne.boyer@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + 2 files changed, 2 insertions(+)