From patchwork Fri Dec 9 15:23:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13069862 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B9C3C4167B for ; Fri, 9 Dec 2022 15:27:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F2E8510E54B; Fri, 9 Dec 2022 15:27:31 +0000 (UTC) Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4D1810E54B for ; Fri, 9 Dec 2022 15:27:29 +0000 (UTC) Received: by mail-pl1-x635.google.com with SMTP id jl24so5213007plb.8 for ; Fri, 09 Dec 2022 07:27:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OfCnS0osLOS8xaWpCmO4LYnynxznfz+nnT8/dn7VQfk=; b=nSJNeITl9fnTfPnvJhvt7rcK/xV7j/NWCI0p9//tsOA/UM56OFpEr7ygGEIbx7Y1No XWJd/V2u6MoDaGZXuAZBIhc/UHZa2e2QokYR6Zih3+5iRVGEpIU3l0EEftElSRDOjPN1 n96YN33rgcOTAZC9jUXZndGbTxC/brxMpVgfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OfCnS0osLOS8xaWpCmO4LYnynxznfz+nnT8/dn7VQfk=; b=Sl0CamaiVVWJawRAI7zOu72Qij3/19hTVBYSMBuPxhBAVUwrFbIq1y6tbHUXtmL2x1 becOczHm8qHvPctBAvGjZyHgeuSDdWqXisudnJN+Ss8zdO9zSdfGxMeVvPvvMljBcr+u nLFVP1pn+O8pK1jyhmZEgS4l5VuEfmZtQdWg0993mRsixgWysbjMu80BidgKdclNI0fc Ez6H3UmCMmz8Hq9DObhUMrIG+KXUfQ+qOEtR0a+Ehs9lX1gMhaVgd4uf6CxQFKsSbVz2 rE2pkMSg1kGUiCs9+N09aCBkluUESiNO7Q6rsuagy8WWanuOLg+M0ZwSSA3NI3JGG1q7 DJkw== X-Gm-Message-State: ANoB5plaig7IjYV7iUVHleaiYjTeleXNCuqINFO2821YuJeEBgFsCO6b K1tifbedOeKwYmeL9CsMxQbi8w== X-Google-Smtp-Source: AA0mqf5RMvL/6/KcRoodcz3nCDPqXEouCFOwfCuTdoOSewQ5pw+uHy3hlJMsbykq4AKHdpBGOhdd1Q== X-Received: by 2002:a17:902:e807:b0:189:63be:8acb with SMTP id u7-20020a170902e80700b0018963be8acbmr8774321plg.59.1670599649351; Fri, 09 Dec 2022 07:27:29 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:6ba1:bbda:c542:ba0b]) by smtp.gmail.com with ESMTPSA id x14-20020a170902ec8e00b00188c5f0f9e9sm1477587plg.199.2022.12.09.07.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 07:27:28 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Adam Ford , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut Subject: [PATCH v9 11/18] drm: bridge: samsung-dsim: Add atomic_check Date: Fri, 9 Dec 2022 20:53:36 +0530 Message-Id: <20221209152343.180139-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221209152343.180139-1-jagan@amarulasolutions.com> References: <20221209152343.180139-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Matteo Lisi , dri-devel@lists.freedesktop.org, NXP Linux Team , linux-amarula , linux-arm-kernel@lists.infradead.org, Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added a comment FIXME for this and updated the active low sync polarities using SAMSUNG_DSIM_TYPE_IMX8MM hw_type. v9: * none v8: * update the comments about sync signals polarities * added clear commit message by including i.MX8M Nano details v7: * fix the hw_type checking logic v6: * none v5: * rebase based new bridge changes [mszyprow] * remove DSIM_QUIRK_FIXUP_SYNC_POL * add hw_type check for sync polarities change. v4: * none v3: * add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup v2: * none v1: * fix mode flags in atomic_check instead of mode_fixup Signed-off-by: Jagan Teki --- drivers/gpu/drm/bridge/samsung-dsim.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index ec3ab679afd9..c79f7dc49e17 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1342,6 +1342,32 @@ static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int samsung_dsim_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct samsung_dsim *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == SAMSUNG_DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void samsung_dsim_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1364,6 +1390,7 @@ static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = samsung_dsim_atomic_check, .atomic_pre_enable = samsung_dsim_atomic_pre_enable, .atomic_enable = samsung_dsim_atomic_enable, .atomic_disable = samsung_dsim_atomic_disable,