From patchwork Wed Dec 14 12:58:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13073076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF8B4C4332F for ; Wed, 14 Dec 2022 13:00:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39D2010E3EE; Wed, 14 Dec 2022 13:00:24 +0000 (UTC) Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47A4410E3E3 for ; Wed, 14 Dec 2022 13:00:07 +0000 (UTC) Received: by mail-pl1-x636.google.com with SMTP id d7so3224435pll.9 for ; Wed, 14 Dec 2022 05:00:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UIrJ0sMj4TBazRS1wROrogpqFN4PzyDsm2y3+TsztNI=; b=DfVAry6sVS7b6KoufU0/aS8JBBcf4zBdG9IUX1IEpCtwD9uPoh9Ukvx7gWt8Q+9VI9 XnELciUawS89l5X5OwPP6chAeC6rFYWNw8/5psr0uGzzw3eqyfMd7ZgqImeQV0UBs7mG k/6q/vNjeRUQ8IepNnjoK67aE1h9qQh0IC8Ss= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIrJ0sMj4TBazRS1wROrogpqFN4PzyDsm2y3+TsztNI=; b=Pci3BEDWfVvL5FOiX995ujiUnu7NSe4nXAQbaimFUyn5j4C0LFLuKMj938a0sCLUj5 nRQdpDfRF2eX0HxJSXQDfBXbzGS+05WFXXwYINErXzzCTlhLEaHKo0XHImhfv5g081T7 24d+cNCXu7UbxzWwKwuMnc1QeNZ0Jb86I/paYYwt5fub5zct0Z+mj47fM8dcpDX1yvuU JW2NNGGAEDFG2nK8GO6MIhiPgQ6bsf70G8heQdcBZ2be4OAsJYPXdtKYLmAqe3ipNVWS CDjCCthItezQ+bsob71XZdJpOhS+0N0UmyhaEJXnMem+XOyjTpUK52icFn74b4d1NZS+ eefg== X-Gm-Message-State: ANoB5plyii0918/7+BaNOV/srlDM2Q3KmD+b76FW/FEHGTCYmQi2c9sZ LNP4peaD3IUaK/c50m9L8D+oAQ== X-Google-Smtp-Source: AA0mqf7B5S2Wce1GSRBZNr7ZG9u/A0cq5Cj0vNwmkLkrf2A5ySS6h2Bjel+ZftQ9XASNwufmKRHKaA== X-Received: by 2002:a05:6a20:6918:b0:9d:efc0:62 with SMTP id q24-20020a056a20691800b0009defc00062mr41746149pzj.10.1671022806323; Wed, 14 Dec 2022 05:00:06 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:5e03:faf:846e:352d]) by smtp.gmail.com with ESMTPSA id ix17-20020a170902f81100b001895f7c8a71sm1838651plb.97.2022.12.14.04.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Dec 2022 05:00:05 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Fancy Fang , Tim Harvey , Michael Nazzareno Trimarchi , Adam Ford , Neil Armstrong , Robert Foss , Laurent Pinchart , Tommaso Merciai , Marek Vasut Subject: [PATCH v10 05/18] drm: exynos: dsi: Mark PHY as optional Date: Wed, 14 Dec 2022 18:28:54 +0530 Message-Id: <20221214125907.376148-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221214125907.376148-1-jagan@amarulasolutions.com> References: <20221214125907.376148-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-samsung-soc@vger.kernel.org, Matteo Lisi , dri-devel@lists.freedesktop.org, NXP Linux Team , linux-amarula , linux-arm-kernel@lists.infradead.org, Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The same Samsung MIPI DSIM master can also be used in NXP's i.MX8M Mini/Nano/Plus SoC. In i.MX8M Mini/Nano/Plus SoC the DSI Phy requires a MIPI DPHY bit to reset in order to activate the PHY and that can be done via upstream i.MX8M blk-ctrl driver. So, mark the phy get as optional. Reviewed-by: Marek Vasut Signed-off-by: Jagan Teki Reviewed-by: Frieder Schrempf --- Changes for v10: - add Plus in commit message - collect Marek RB Changes for v9, v8, v7, v6, v5, v4, v3, v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 4a165764121d..5918d31127aa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1687,7 +1687,7 @@ static int exynos_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->reg_base)) return PTR_ERR(dsi->reg_base); - dsi->phy = devm_phy_get(dev, "dsim"); + dsi->phy = devm_phy_optional_get(dev, "dsim"); if (IS_ERR(dsi->phy)) { dev_info(dev, "failed to get dsim phy\n"); return PTR_ERR(dsi->phy);