From patchwork Thu Jan 5 03:42:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13089386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50D28C4708D for ; Thu, 5 Jan 2023 03:44:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B482210E65A; Thu, 5 Jan 2023 03:44:33 +0000 (UTC) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2041.outbound.protection.outlook.com [40.107.223.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 50CEE10E65A; Thu, 5 Jan 2023 03:44:28 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lezO7seOpCphMaVCE0oaMiM942e/r82YTHKIopv9bNpaStz9zFHQTIbCFgTFXGtCELYetzNRuPflAjTZq/56s9Wt/eAVJuIBm5vXdaH/aGm8O2zgSigQCpwPXN8l+Zq0Cs2LrDygMIsliXH1sTEYBjOMxhnbY4YgKgmI49pCCKcBX/iLXhO5XTo7G3KhqasTENxwEO+lijaHZ7+fDHAS0Ti3gGbqqUDujKDZSywR9X2LzuoXpxoBlSDyHBO3az4n2k6Aa80TxnwASuxMVWUNnzpYXuVoP+wwcA5ooyZMS3dPb7qOZlZA/cVyIE1GuOZk7KONQ6iiE2FiPRAo5+Psqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Dl9apohMcnVXuwNt0GxVN7v2EwcLvg0hCwEDOcm3Jt4=; b=nvKLTDO0jlHTWINBOESjhlejbeuSKdhLlXXsyyL6mPMj6bsjNnfM3sfjz/ifD5mz61Mci3kbVkqmh4K+ZKw4OaCJevvolZwidIRXGrvGzpdwHtQk15NqUEswU4Mogl6SB8rQ9v2qQnxJX6Q/awQrjYGjMeQd8Zay4g1oIZMKg+9ZWEwMTvMus6Mhh/G/yPBZn/dqb7z6PeYCDHLrvbUlOa0qd5SM7mCWhTD4cGyJL7QDbnJbxY1cH92JRYv4n1uNn/tiolS489i3djPqV9rlpIrW4sh+Aexmr6xNlKep9tQ51Skth7WgGq85HSdcfjdwzQJgBczIWgKATnzqDypZHA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Dl9apohMcnVXuwNt0GxVN7v2EwcLvg0hCwEDOcm3Jt4=; b=x32JPKEIgIF3MIS+2hAADfLGufkUWka71jhpVaKdD5Ys+LtMKcpzPC+zeOlp/Pr8RY+EzleW7xe8Voaq1fV6uS5arvp5nggeub1GcyAOsByv0UFFy0EBfOE3iUOmW4Vp8AchihRmXKM7resq1tmy535JGiBFFqLcTjXLzj6bqas= Received: from BN9PR03CA0624.namprd03.prod.outlook.com (2603:10b6:408:106::29) by MW3PR12MB4476.namprd12.prod.outlook.com (2603:10b6:303:2d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5944.19; Thu, 5 Jan 2023 03:44:23 +0000 Received: from BN8NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:408:106:cafe::35) by BN9PR03CA0624.outlook.office365.com (2603:10b6:408:106::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5986.14 via Frontend Transport; Thu, 5 Jan 2023 03:44:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5944.17 via Frontend Transport; Thu, 5 Jan 2023 03:44:22 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 4 Jan 2023 21:44:19 -0600 From: Mario Limonciello To: Alex Deucher , Subject: [PATCH v6 16/45] drm/amd: Use `amdgpu_ucode_*` helpers for GFX10 Date: Wed, 4 Jan 2023 21:42:50 -0600 Message-ID: <20230105034327.1439-17-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230105034327.1439-1-mario.limonciello@amd.com> References: <20230105034327.1439-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT065:EE_|MW3PR12MB4476:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f9f5e89-7c14-4cf8-c098-08daeecf2229 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +UOrvsZCQhk/nKiY/lHKB4V67DUk6mK7n8l6yCAHOY/AJACF2S2R5vlL86C7sdNDv7+8xC94CUw1K2MIa4yhJaKm1ES1T4AGmxHVYbYtubn+ZhOffHMZzeZV3K4kmoVPgPRlck3vl7C8kHdmsjJyiGW/c2SZ5vQrTcI2UDZCs6NgyocLnnVj9MCo4Pp/wdVyxuqL0PsZEYrOddjRRQPdGS8RGfdBGCcNXxFMpv6N1qsxsg9KoD2cYJVEI9YeLBYQMLdSJ+SedO8RUYXMbX+zWY0kKoXZ1Opq3A13e6JhMcjTyiV5MzbMXHVTKTI+GzMryZXVgbq9WkedgNhdaW7RKflxTsaPB0Wt2P5CIqSaXqQKSHqcQteZlueXVdMhvNG9nSjp3yH154lord0xUt7dDTJI02yuiuuZM3BaoQxHx6gA1R9CJqm0zjBVa0m1ezcfB9YW3Ch5Qf2vYCGPLAaMLgFUBe2oaPVGFOIU0BsGIFawTAwkF20xpR9ox/TbolZT3WHq7rNsnDmro4UeQpf4+WYWxc8D+AsBTtNSwi0x+7at91YamkYMOGkicQX9cd5lq8NIP3T1uGpahc/6HqlDNUph3yBb/CIWCU4scB/rSBzLnilx4fNAyQ04t6via4Kd1XOcpBH4N655WHg862if4MrlKu9kL+IQG3Xa/lV8wG2l6WLDwfUU8f7UT7AKr5z9pkG4d4/JGq89ehIHG1uomZ2bamYlw9RXzkB9+g5jWPcmRHMkpQn8/atPPmLR0ifW1kJPoNR8KwSoBQGE4s6T0Q== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199015)(40470700004)(46966006)(36840700001)(70206006)(44832011)(8936002)(5660300002)(70586007)(316002)(41300700001)(2906002)(54906003)(8676002)(4326008)(478600001)(36756003)(82310400005)(110136005)(6666004)(36860700001)(26005)(83380400001)(2616005)(1076003)(16526019)(47076005)(426003)(186003)(7696005)(82740400003)(86362001)(336012)(40480700001)(356005)(40460700003)(81166007)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jan 2023 03:44:22.4680 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f9f5e89-7c14-4cf8-c098-08daeecf2229 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4476 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Pan, Xinhui" , Lazar Lijo , Javier Martinez Canillas , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, Carlos Soriano Sanchez , christian.koenig@amd.com, Mario Limonciello Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The `amdgpu_ucode_request` helper will ensure that the return code for missing firmware is -ENODEV so that early_init can fail. The `amdgpu_ucode_release` helper is for symmetry on unload. Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello --- v5->v6: * Adjust for amdgpu_ucode_release argument change --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 71 ++++++++------------------ 1 file changed, 20 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 49d34c7bbf20..140bb18ff768 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -3891,18 +3891,12 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) { - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); kfree(adev->gfx.rlc.register_list_format); } @@ -4030,41 +4024,31 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.pfp_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.me_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.ce_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); if (!amdgpu_sriov_vf(adev)) { snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); - err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); - if (err) - goto out; + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); /* don't check this. There are apparently firmwares in the wild with * incorrect size in the header */ - err = amdgpu_ucode_validate(adev->gfx.rlc_fw); + if (err == -ENODEV) + goto out; if (err) dev_dbg(adev->dev, "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", @@ -4078,21 +4062,15 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) } snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); - if (err) - goto out; - err = amdgpu_ucode_validate(adev->gfx.mec_fw); + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); if (err) goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); } else { @@ -4103,21 +4081,12 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) gfx_v10_0_check_fw_write_wait(adev); out: if (err) { - dev_err(adev->dev, - "gfx10: Failed to init firmware \"%s\"\n", - fw_name); - release_firmware(adev->gfx.pfp_fw); - adev->gfx.pfp_fw = NULL; - release_firmware(adev->gfx.me_fw); - adev->gfx.me_fw = NULL; - release_firmware(adev->gfx.ce_fw); - adev->gfx.ce_fw = NULL; - release_firmware(adev->gfx.rlc_fw); - adev->gfx.rlc_fw = NULL; - release_firmware(adev->gfx.mec_fw); - adev->gfx.mec_fw = NULL; - release_firmware(adev->gfx.mec2_fw); - adev->gfx.mec2_fw = NULL; + amdgpu_ucode_release(&adev->gfx.pfp_fw); + amdgpu_ucode_release(&adev->gfx.me_fw); + amdgpu_ucode_release(&adev->gfx.ce_fw); + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + amdgpu_ucode_release(&adev->gfx.mec2_fw); } gfx_v10_0_check_gfxoff_flag(adev);