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Thu, 19 Jan 2023 15:52:12 -0800 Received: from hwentlanryzen.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 19 Jan 2023 17:52:11 -0600 From: Harry Wentland To: , Subject: [PATCH 2/7] drm/amdgpu/display/mst: limit payload to be updated one by one Date: Thu, 19 Jan 2023 18:51:55 -0500 Message-ID: <20230119235200.441386-3-harry.wentland@amd.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119235200.441386-1-harry.wentland@amd.com> References: <20230119235200.441386-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT104:EE_|CH2PR12MB4230:EE_ X-MS-Office365-Filtering-Correlation-Id: 4abf48f9-3148-4733-e8c0-08dafa783002 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MAhQqxP9rb8TFX0sxX6t1Pwh/7UZ/e4PpcYt3HikM5BOj8QRkmGKKqIStwNs22L1b6qAJKJ4h0maf4GlJVS1eYqMX0YrYtBww6RJ6Zk/15+Qkcdmh75/a9vas08VX4E7zprLaUucMRt9iBXpT7+BCci370vaz0HQNSj06giKqHNr15O4RbU86W+kxYL2gRzko7TqpR5Ny+wKuXH3j1U7plIu+Xi71LPhKya1UFuJZ9UUtNMHu2bl3EFNmo7JAtPcMKVpm6QK0DHvxrYieXm1ksICYdZZXhqQlgJwvYPPsOSOxZmT5+ghuEYSWjbCXu1pQ2C+kyU9nRole0PDuQzKq2p2DRyxopl3P8M4VfN54bfUDs/YFrFFS7Dei4TfixRHQEqJpZ71WyF8JLC8OdvjRZOPqUDTEF1DCKqkqYHqOhS6ch35q4pBC+ozq511AjK19rR8Gxnit/cZR/l6SStw8+VpMjBGoqzjW8oNAzSpSQbk2uOU5hFwmEJnlpEW625QCiasSna3YW91wEX5sCSTx1UDAD11ToKtXuM6E/tz+IB+YhozjFPeEKnmbtnXPnHs9PJXDrrDmpoHygLu8dJop5e6wQ4cy4/qzhOcNqQDwWa8+wEfbPJCd2x4q+80VMReOy0ViKr9c3yNRu/pTX8xh/t3mJ+4wahDyvL3J/qNeMr/2MVK6k8NSPo2+TSGcGZB X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199015)(40470700004)(46966006)(36840700001)(41300700001)(4326008)(6666004)(26005)(8676002)(70586007)(8936002)(70206006)(36756003)(82310400005)(336012)(2906002)(36860700001)(44832011)(40460700003)(5660300002)(15650500001)(110136005)(316002)(2616005)(54906003)(7696005)(40480700001)(86362001)(966005)(186003)(478600001)(356005)(81166007)(1076003)(83380400001)(82740400003)(426003)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 23:52:13.4081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4abf48f9-3148-4733-e8c0-08dafa783002 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT104.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4230 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stable@vger.kernel.org, stanislav.lisovskiy@intel.com, jerry.zuo@amd.com, bskeggs@redhat.com, Wayne.Lin@amd.com, mario.limonciello@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Wayne Lin [Why] amdgpu expects to update payload table for one stream one time by calling dm_helpers_dp_mst_write_payload_allocation_table(). Currently, it get modified to try to update HW payload table at once by referring mst_state. [How] This is just a quick workaround. Should find way to remove the temporary struct dc_dp_mst_stream_allocation_table later if set struct link_mst_stream_allocatio directly is possible. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Wayne Lin Signed-off-by: Harry Wentland Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") Cc: stable@vger.kernel.org # 6.1 Acked-by: Harry Wentland --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 51 ++++++++++++++----- 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 6994c9a1ed85..5cff56bb8f56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -120,23 +120,50 @@ enum dc_edid_status dm_helpers_parse_edid_caps( } static void -fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state, - struct amdgpu_dm_connector *aconnector, +fill_dc_mst_payload_table_from_drm(struct dc_link *link, + bool enable, + struct drm_dp_mst_atomic_payload *target_payload, struct dc_dp_mst_stream_allocation_table *table) { struct dc_dp_mst_stream_allocation_table new_table = { 0 }; struct dc_dp_mst_stream_allocation *sa; - struct drm_dp_mst_atomic_payload *payload; + struct link_mst_stream_allocation_table copy_of_link_table = + link->mst_stream_alloc_table; + + int i; + int current_hw_table_stream_cnt = copy_of_link_table.stream_count; + struct link_mst_stream_allocation *dc_alloc; + + /* TODO: refactor to set link->mst_stream_alloc_table directly if possible.*/ + if (enable) { + dc_alloc = + ©_of_link_table.stream_allocations[current_hw_table_stream_cnt]; + dc_alloc->vcp_id = target_payload->vcpi; + dc_alloc->slot_count = target_payload->time_slots; + } else { + for (i = 0; i < copy_of_link_table.stream_count; i++) { + dc_alloc = + ©_of_link_table.stream_allocations[i]; + + if (dc_alloc->vcp_id == target_payload->vcpi) { + dc_alloc->vcp_id = 0; + dc_alloc->slot_count = 0; + break; + } + } + ASSERT(i != copy_of_link_table.stream_count); + } /* Fill payload info*/ - list_for_each_entry(payload, &mst_state->payloads, next) { - if (payload->delete) - continue; - - sa = &new_table.stream_allocations[new_table.stream_count]; - sa->slot_count = payload->time_slots; - sa->vcp_id = payload->vcpi; - new_table.stream_count++; + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + dc_alloc = + ©_of_link_table.stream_allocations[i]; + if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) { + sa = &new_table.stream_allocations[new_table.stream_count]; + sa->slot_count = dc_alloc->slot_count; + sa->vcp_id = dc_alloc->vcp_id; + new_table.stream_count++; + } } /* Overwrite the old table */ @@ -185,7 +212,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( * AUX message. The sequence is slot 1-63 allocated sequence for each * stream. AMD ASIC stream slot allocation should follow the same * sequence. copy DRM MST allocation to dc */ - fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table); + fill_dc_mst_payload_table_from_drm(stream->link, enable, payload, proposed_table); return true; }