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Thu, 19 Jan 2023 17:52:19 -0600 Received: from hwentlanryzen.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Thu, 19 Jan 2023 17:52:18 -0600 From: Harry Wentland To: , Subject: [PATCH 7/7] drm/amdgpu/display/mst: adjust the logic in 2nd phase of updating payload Date: Thu, 19 Jan 2023 18:52:00 -0500 Message-ID: <20230119235200.441386-8-harry.wentland@amd.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119235200.441386-1-harry.wentland@amd.com> References: <20230119235200.441386-1-harry.wentland@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT006:EE_|SA1PR12MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: cae02892-51e0-48a8-7afc-08dafa783419 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wefAZEeK8AWLOsdxzRP6oP8tgXYsmAH5EdNF60naL/8Nv8j/qXb1m+K9Zq+1+uKZyGroC1qCAVzIZ30x7h1whK01H+mDDuXUQqCIXKfDldZ+YJb8wfbJc3wQxeyTKGWugt1NSRGQqy3pJHuJJlNRTp7+wv9Dwj6PHRx1FBvN6fCn3flX1X7ep/D+rGMFpxALmfEITuA1M4mftQ4gJ/2rmu8DmWNkFpgcU3TzIpahIPu5KoE8cHHWHwTJt7vur5j69hhH29aNMiwEc/AJ3tpFAwbCSCDjL9O6vWvSkwNfsTlea010snPTUsGORGvzYEuzjWQ9ZhAFCcfLfRjnuAoQtXyTgPDpztdnfo2pIV4lDRiZ8TG6x6stZAS2KbBusuUtEjtPNd60tE7ig5PYuqF4mNA6xs9SmApA5vn05+1c1CUucC9KFmdan2tC3V16eR6Lbvaas8ls9czLcCMZTzwM4c9eiXuwaC9ZVVQ12VGvJisVvEDopl0ZnCfSlybVUaRYjV/JZqtF4rriXDXG7b76dfx1+tyMQDpBuaw+z+IJwd4VzCJT06zDCUxSlXdOU5orf8KzcjVNPNDbFI+wf5GzVBWJkCl2dPYkcz1Ey6opjN8HtGHxuNT6PRM70DlfKnEXuSh9fSFrWX56NP12NIG1yBByR30MJBaiU7+aIPoTMrO0I9EQRglJgIBP8haHt2VtXRA4r8jJgRERnfmHehvzU9zgh6aOB9NbSFQ829xO6yE= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199015)(46966006)(40470700004)(36840700001)(83380400001)(5660300002)(82310400005)(86362001)(426003)(356005)(81166007)(2906002)(336012)(44832011)(1076003)(47076005)(8936002)(2616005)(82740400003)(4326008)(8676002)(36756003)(7696005)(40460700003)(186003)(70586007)(70206006)(26005)(41300700001)(36860700001)(478600001)(40480700001)(6666004)(54906003)(110136005)(316002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2023 23:52:20.2669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cae02892-51e0-48a8-7afc-08dafa783419 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stable@vger.kernel.org, stanislav.lisovskiy@intel.com, jerry.zuo@amd.com, bskeggs@redhat.com, Wayne.Lin@amd.com, mario.limonciello@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Wayne Lin [why & how] adjust the coding in dm_helpers_dp_mst_send_payload_allocation() for reading easily. Signed-off-by: Wayne Lin Signed-off-by: Harry Wentland Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7aff7eb13ea2..fba6a57158cf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -274,6 +274,7 @@ bool dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_atomic_payload *payload; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; + int ret = 0; aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; @@ -290,7 +291,10 @@ bool dm_helpers_dp_mst_send_payload_allocation( clr_flag = MST_ALLOCATE_NEW_PAYLOAD; } - if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) { + if (enable) + ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload); + + if (ret) { amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, false); } else {