| Message ID | 20230120043844.3761895-3-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC fractional bpp support | expand |
On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: > For MST the bpc is hardcoded to 8, and pipe bpp to 24. > So avoid forcing DSC bpc for MST case. It's likely better to warn and ignore the debug flag than to bail out. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ > 2 files changed, 13 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 93aebd3683a4..3d828ea0894d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, > if (!intel_dp_supports_dsc(intel_dp, pipe_config)) > return -EINVAL; > > - if (compute_pipe_bpp) > + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { > + pipe_bpp = intel_dp->force_dsc_bpc * 3; > + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); > + } else if (compute_pipe_bpp) { > pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); > - else > + } else { > pipe_bpp = pipe_config->pipe_bpp; > - > - if (intel_dp->force_dsc_bpc) { > - pipe_bpp = intel_dp->force_dsc_bpc * 3; > - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); > } > > /* Min Input BPC for ICL+ is 8 */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 8b0e4defa3f1..9be04c60cced 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, > /* enable compression if the mode doesn't fit available BW */ > drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); > if (ret || intel_dp->force_dsc_en) { > + if (intel_dp->force_dsc_bpc) { > + /* > + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above, > + * Avoid force BPC for now. > + */ > + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n"); > + return -EINVAL; > + } > /* > * Try to get at least some timeslots and then see, if > * we can fit there with DSC.
On 1/24/2023 9:53 PM, Jani Nikula wrote: > On Fri, 20 Jan 2023, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote: >> For MST the bpc is hardcoded to 8, and pipe bpp to 24. >> So avoid forcing DSC bpc for MST case. > It's likely better to warn and ignore the debug flag than to bail out. Hmm..but then the test using this flag will not come to know that bpc it wanted to force, was indeed used. Currently there is no way to read the bpc that was selected by the driver, and so the test can try to force DSC, and the bpc and rely on whether the ioctl passes or fails. Regards, Ankit > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ >> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ >> 2 files changed, 13 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index 93aebd3683a4..3d828ea0894d 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, >> if (!intel_dp_supports_dsc(intel_dp, pipe_config)) >> return -EINVAL; >> >> - if (compute_pipe_bpp) >> + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { >> + pipe_bpp = intel_dp->force_dsc_bpc * 3; >> + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); >> + } else if (compute_pipe_bpp) { >> pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); >> - else >> + } else { >> pipe_bpp = pipe_config->pipe_bpp; >> - >> - if (intel_dp->force_dsc_bpc) { >> - pipe_bpp = intel_dp->force_dsc_bpc * 3; >> - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); >> } >> >> /* Min Input BPC for ICL+ is 8 */ >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> index 8b0e4defa3f1..9be04c60cced 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c >> @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, >> /* enable compression if the mode doesn't fit available BW */ >> drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); >> if (ret || intel_dp->force_dsc_en) { >> + if (intel_dp->force_dsc_bpc) { >> + /* >> + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above, >> + * Avoid force BPC for now. >> + */ >> + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n"); >> + return -EINVAL; >> + } >> /* >> * Try to get at least some timeslots and then see, if >> * we can fit there with DSC.
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 93aebd3683a4..3d828ea0894d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1500,14 +1500,13 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; - if (compute_pipe_bpp) + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { + pipe_bpp = intel_dp->force_dsc_bpc * 3; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d\n", pipe_bpp); + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; - - if (intel_dp->force_dsc_bpc) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); } /* Min Input BPC for ICL+ is 8 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 8b0e4defa3f1..9be04c60cced 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -325,6 +325,14 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, /* enable compression if the mode doesn't fit available BW */ drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); if (ret || intel_dp->force_dsc_en) { + if (intel_dp->force_dsc_bpc) { + /* + * FIXME: As bpc is hardcoed to 8 bpc as mentioned above, + * Avoid force BPC for now. + */ + drm_dbg_kms(&dev_priv->drm, "Cannot Force BPC for MST\n"); + return -EINVAL; + } /* * Try to get at least some timeslots and then see, if * we can fit there with DSC.
For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++ 2 files changed, 13 insertions(+), 6 deletions(-)