From patchwork Wed Jan 25 08:06:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Previn X-Patchwork-Id: 13115076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5BC16C27C76 for ; Wed, 25 Jan 2023 08:07:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E880D10E745; Wed, 25 Jan 2023 08:07:02 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3ED410E73A; Wed, 25 Jan 2023 08:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674634015; x=1706170015; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4jIM+rAvkJsfNZoozqXpV3F6jtWvzuAhTZfKZs20pEs=; b=KwAEGvDS2DHneN51BCVdwWb7txSh+Y3PpQpkcl54RNBOnCI5MY2NuyXb V7yAChPcde9SM86dz2cA2pm90Q7/e93oCBM+TGnV46/Di1KhG9/1jzWrh 4ijjSkvZvm8nVz5/AnF+VWA3LTTz8PmEfxONEi5Ebrb+JEuVnuKGXXNjE J507cJaPLol5AYP7gyFbd3v5hp6CEbvU5k59K/qw9rNbq0b8ZsktebJwq PH2jv5dhBZjTiT07vxEyWvG6As3EJA9PetqflHSouRbFx7225f2/RYOe3 kUkhAsUrJOUPjHkHuwMTIjzglBe4vYNS4RXQNIyLxtg5D9GJNJMv36Zax A==; X-IronPort-AV: E=McAfee;i="6500,9779,10600"; a="310079373" X-IronPort-AV: E=Sophos;i="5.97,244,1669104000"; d="scan'208";a="310079373" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jan 2023 00:06:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10600"; a="991180688" X-IronPort-AV: E=Sophos;i="5.97,244,1669104000"; d="scan'208";a="991180688" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga005.fm.intel.com with ESMTP; 25 Jan 2023 00:06:54 -0800 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v3 6/8] drm/i915/pxp: MTL-KCR interrupt ctrl's are in GT-0 Date: Wed, 25 Jan 2023 00:06:49 -0800 Message-Id: <20230125080651.100223-7-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230125080651.100223-1-alan.previn.teres.alexis@intel.com> References: <20230125080651.100223-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juston Li , Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Despite KCR subsystem being in the media-tile (close to the GSC-CS), the IRQ controls for it are on GT-0 with other global IRQ controls. Thus, add a helper for KCR hw interrupt enable/disable functions to get the correct gt structure (for uncore) for MTL. In the helper, we get GT-0's handle for uncore when touching IRQ registers despite the pxp->ctrl_gt being the media-tile. No difference for legacy of course. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +++++++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +++++++ 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4b8e70caa3ad..9f6e300486b4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -44,7 +44,7 @@ static int pxp_terminate_get(void *data, u64 *val) static int pxp_terminate_set(void *data, u64 val) { struct intel_pxp *pxp = data; - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); if (!intel_pxp_is_active(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 91e9622c07d0..3a725397349f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -4,10 +4,12 @@ */ #include +#include "gt/intel_gt.h" #include "gt/intel_gt_irq.h" #include "gt/intel_gt_regs.h" #include "gt/intel_gt_types.h" +#include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" @@ -17,6 +19,22 @@ #include "intel_pxp_types.h" #include "intel_runtime_pm.h" +/** + * intel_pxp_get_irq_gt - Find the correct GT that owns KCR interrupts + * @pxp: pointer to pxp struct + * + * For platforms with a single GT, we return the pxp->ctrl_gt (as expected) + * but for MTL+ that has a media-tile, although the KCR engine is in the + * media-tile (i.e. pxp->ctrl_gt), the IRQ controls are on the root tile. + * In the end, we don't use pxp->ctrl_gt for IRQ, we always return root gt. + */ +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + WARN_ON_ONCE(!pxp->ctrl_gt->i915->media_gt && !gt_is_root(pxp->ctrl_gt)); + + return to_gt(pxp->ctrl_gt->i915); +} + /** * intel_pxp_irq_handler - Handles PXP interrupts. * @pxp: pointer to pxp struct @@ -29,7 +47,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) return; - gt = pxp->ctrl_gt; + gt = intel_pxp_get_irq_gt(pxp); lockdep_assert_held(gt->irq_lock); @@ -68,7 +86,7 @@ static inline void pxp_irq_reset(struct intel_gt *gt) void intel_pxp_irq_enable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); spin_lock_irq(gt->irq_lock); @@ -83,7 +101,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) void intel_pxp_irq_disable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); /* * We always need to submit a global termination when we re-enable the diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h index 8c292dc86f68..eea87c9eb62b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h @@ -9,6 +9,7 @@ #include struct intel_pxp; +struct intel_gt; #define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1) #define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2) @@ -23,6 +24,8 @@ struct intel_pxp; void intel_pxp_irq_enable(struct intel_pxp *pxp); void intel_pxp_irq_disable(struct intel_pxp *pxp); void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp); + #else static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { @@ -35,6 +38,11 @@ static inline void intel_pxp_irq_enable(struct intel_pxp *pxp) static inline void intel_pxp_irq_disable(struct intel_pxp *pxp) { } + +static inline struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + return NULL; +} #endif #endif /* __INTEL_PXP_IRQ_H__ */