From patchwork Tue Jan 31 20:08:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13123377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF204C636CC for ; Tue, 31 Jan 2023 20:09:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE64010E394; Tue, 31 Jan 2023 20:09:07 +0000 (UTC) Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by gabe.freedesktop.org (Postfix) with ESMTPS id F18FB10E393 for ; Tue, 31 Jan 2023 20:08:59 +0000 (UTC) Received: by mail-qt1-x833.google.com with SMTP id z5so5048694qtn.8 for ; Tue, 31 Jan 2023 12:08:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lyl33WAUjvF8alq7KuyZ+uiGuXUTkE3ON8jKXV0pXVs=; b=cPD7dmab1R36OliQIiJ0KMkSesyvi36UTEUoIdOLjd5LEuk92j90nMV2uUbtuO56/Q LI/q3qbvl3i+0OCMXCGGd3UvQiezs7dGJIfsVtutnXb7KPASxP07w18Qts6ctI6tGAas GlTBhB7q63BRCv6j0+m2csTy0EUrhIo3hUR1Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lyl33WAUjvF8alq7KuyZ+uiGuXUTkE3ON8jKXV0pXVs=; b=7HxKv11wp1gvZ7gLviEtTs7Ebp7W0HhQBhKicxfqsYsZ/AB5jhNMQ8GlmlVlBlNPa/ FTNnrF+wEM6BtxpFqi2KcZdkOlYRQvENzIVxIO1vUfyXHzEeoepn7Ex9mcN6rREYAUZA +cchwONItNdH+7iti4PYyinBPUYYNz3RPpEbv7nV8+5kWsc207Ixd7c3cJAw7WeGMCdM 2K1PJVKopcAzhON/Az2NKMo8QsyLtGXUJAZaugy1HoTd13shdU6Se/HczSALXc3kaN6S +dwH6VzA+jtZ22PerhPUpQp6o6NNK5/8zJPdA1oGsYxblr4oLMD1XuPOQMfmefCfvGT0 C2lQ== X-Gm-Message-State: AO0yUKV4mArHh4PqNx6hcSH4yX6cMyy0NP0PuC4M+aeRmmiFwbQZijx0 HibPq/VFV41Y9zvwX++LCXz3zw== X-Google-Smtp-Source: AK7set+6cXk0xnrFR+MhMHFcgZTHW1W3yQPE6bY9vNoZhDrj897UGwGWYzAYKFXqq6HMLigMuZA2rA== X-Received: by 2002:ac8:5c0c:0:b0:3b8:2ce4:3e9 with SMTP id i12-20020ac85c0c000000b003b82ce403e9mr29384821qti.32.1675195738998; Tue, 31 Jan 2023 12:08:58 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:502d:723:d741:14cd]) by smtp.gmail.com with ESMTPSA id m186-20020a37bcc3000000b007068b49b8absm10658782qkf.62.2023.01.31.12.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:08:58 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/mediatek: Add support for AR30 and BA30 overlays Date: Tue, 31 Jan 2023 15:08:42 -0500 Message-Id: <20230131200842.341272-3-greenjustin@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog In-Reply-To: <20230131200842.341272-1-greenjustin@chromium.org> References: <20230131200842.341272-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, Justin Green , airlied@linux.ie, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for overlays with pixel formats AR30 and BA30 on MT8195. Tested using "modetest -P" on an MT8195 device. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 49 ++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8743c8047dc9..cd2f9a156456 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -80,6 +85,22 @@ static const u32 mt8173_formats[] = { DRM_FORMAT_YUYV, }; +static const u32 mt8195_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -218,6 +239,27 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -332,9 +374,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -418,6 +462,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); } @@ -583,8 +628,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, - .formats = mt8173_formats, - .num_formats = ARRAY_SIZE(mt8173_formats), + .formats = mt8195_formats, + .num_formats = ARRAY_SIZE(mt8195_formats), }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {