From patchwork Fri Feb 10 14:44:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13135867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B3B8C05027 for ; Fri, 10 Feb 2023 14:44:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 890A310ED52; Fri, 10 Feb 2023 14:44:34 +0000 (UTC) Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5428510ED4E for ; Fri, 10 Feb 2023 14:44:32 +0000 (UTC) Received: by mail-wm1-x32a.google.com with SMTP id r18so3974036wmq.5 for ; Fri, 10 Feb 2023 06:44:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ve8TPSXCg5Pm5cVBZiDNGOJIRFMbfy8PNTtvb1lSqUA=; b=j5hHSt5Sm8TVnbY14lI7SvNqqP5RRD/LJYeUaueV7C/e1k3PkV/B4rF2yCmkjceN0B AzJCd34OYDVwBhSXiKmfVTMo3l74jeI5t1AuAa+Y5MpQLTwhZCzPTY2To/Xgg3b/v1iK CgHNuugoMK9BnF+fJ1xxVdgk8lvzS6QMCVuZMrqc6Jv0kPkBaq4o8ZxnAY2BFYWLLUF9 m/tt70xa76uO2xD3udohVG+jJvFR9PdCffffaV1egwr2A6lAuU3A2SNe03XCCAo7Mz1k fKTyVXI4A517BUrYLwL9akxD0TBJvPKMDUqRMW9SjjgVGncuwZlLD0oaQ89EcOJTg2RA Ep7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ve8TPSXCg5Pm5cVBZiDNGOJIRFMbfy8PNTtvb1lSqUA=; b=CE4kZRn++bCOjKW2BxLeqIi8OseEwDys6Z4LAAO7uibvocONiahPQu+S2wjvxSKZhb 5Zl/yLqqd+JL0MEi95hGaxCHGrdnIaUI8C3jlzQLFNBA/yBSxtzw0UCkX2ZICwIq/7cN rv7iWJLDcP9Ndo4uWG10VhyZGLMXa0x/1lmkihHc+rhBNUF/eJEYqLnc3SxEKuRVW7hz /LXV+8pUapcRrrs4VbM3bzu1AKeBCF1j060ryUiZWP5RLdJofSjWHIczAwAYDSRRD/Z6 2H+kDewoUOknN/+UM+UadGjVQz2edCx8yrc9ZS8DE+UXagISsF0tk26JB99eK2pFICRV +Yng== X-Gm-Message-State: AO0yUKU4DsmpSLztJ5rQLK2UIxgzejidJE42Yxcs8V9ODdvTtHVKGuyx F4XqwzHLhhq69ZyjbgyXupnwlQ== X-Google-Smtp-Source: AK7set81jZLTE303M9v5g8qn7rcNQqLgH0xV789PoXp7tStGUMbSbioGvuHVi9mLmQsQ30bo6hP9cg== X-Received: by 2002:a05:600c:130f:b0:3dc:4313:fd1e with SMTP id j15-20020a05600c130f00b003dc4313fd1emr12747567wmf.34.1676040270750; Fri, 10 Feb 2023 06:44:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id l40-20020a05600c1d2800b003dd1b00bd9asm6103000wms.32.2023.02.10.06.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 06:44:30 -0800 (PST) From: Neil Armstrong Date: Fri, 10 Feb 2023 15:44:23 +0100 Subject: [PATCH v3 3/5] arm64: dts: qcom: sm8350: add dp controller MIME-Version: 1.0 Message-Id: <20230206-topic-sm8450-upstream-dp-controller-v3-3-636ef9e99932@linaro.org> References: <20230206-topic-sm8450-upstream-dp-controller-v3-0-636ef9e99932@linaro.org> In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v3-0-636ef9e99932@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio X-Mailer: b4 0.12.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the Display Port controller subnode to the MDSS node. Tested-by: Dmitry Baryshkov #SM8350-HDK Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 6638704ff469..f48523790883 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2405,6 +2405,85 @@ dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; + }; + }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; };