From patchwork Fri Mar 17 15:06:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13179170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EABEFC7619A for ; Fri, 17 Mar 2023 15:06:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5102410EF30; Fri, 17 Mar 2023 15:06:54 +0000 (UTC) Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by gabe.freedesktop.org (Postfix) with ESMTPS id C252810E3C3 for ; Fri, 17 Mar 2023 15:06:38 +0000 (UTC) Received: by mail-wr1-x430.google.com with SMTP id v25so1264618wra.12 for ; Fri, 17 Mar 2023 08:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679065597; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=h3MpIIR59Oboc27guGIQgznAsN/GbmHsEBoo+9TZbgU=; b=yfmhd1me+B8fXpkDjZGTCavH8W9UJwA84OtbRdIBXiqnlk37G4nmu1wwuoSKQruoUI UL8C6jfrKljwg92VXzgvm0+UppvkbX2qQPBU+UWft2XjQRzg2LA4MS0xZqiQISj9x40p IiM3QhYCM1RYY+fMheaOTPpJHmzf859mwg0Nwec1+8Jwf9qzZnTXDqZaBEBc8IrsE3n+ EXevsQkT5tK37iO+flFB19E2RQz3xhdrwgkMT42kUGb0TGe8kluUElBELHz69ZU9ADbZ IVZ4ZmkJC1xWms5NM6x0CdOXW0IfcddUsILXStiICaRqvsVb4fmY4FEUNVhbnZ6itLTj bPAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679065597; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h3MpIIR59Oboc27guGIQgznAsN/GbmHsEBoo+9TZbgU=; b=z80Z9h18+KwfwG/xbvICCU+B/7oHligLpY6nCw7t+ESI+J+o2vacDzDSBmG6kMjROU rIhL0UhVzpbIB6AnMIqlu4hd17sn4GWa1Q64YLYnTtooDcv/YIkuu/BxOyrcb7HKgxQn fz3rvNzrbjAA5ogaiL49GJY6ycqIwZtf7Ml34nwbxxk2zgY1i1InKd2LAVEtIJz0iKGG kv/dqUF1bhruZcf7O6fCA0CSszxxELzkZuQaqlTQOLh3DsrB6kI/EJIKNjhbAauUvHj/ YqV3sHGNiMcZ3LbdEoVSK0WYYW63TMZbYjlnVv++JRmllfTqV5bQgw6hsm0ZQxEZGLtk n6fg== X-Gm-Message-State: AO0yUKUIZoI4Ico0yRHgOV07W0kmp4ztgv4DpYXa/wP/RRCq4HSmzHWy +4gIrE8liX37SzPTFdy1khHrTg== X-Google-Smtp-Source: AK7set+kHcBHMMA/47EIh+H7feKkHNaYPM5p8JaGSyhEMUoAMzAci4OSwtZ+BnhSItaVUIDRDFyV6w== X-Received: by 2002:a05:6000:1187:b0:2cf:e849:e13c with SMTP id g7-20020a056000118700b002cfe849e13cmr7750339wrx.61.1679065597206; Fri, 17 Mar 2023 08:06:37 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id f13-20020a5d58ed000000b002c5493a17efsm2187902wrd.25.2023.03.17.08.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 08:06:36 -0700 (PDT) From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:34 +0100 Subject: [PATCH v6 3/5] arm64: dts: qcom: sm8350: add dp controller MIME-Version: 1.0 Message-Id: <20230206-topic-sm8450-upstream-dp-controller-v6-3-d78313cbc41d@linaro.org> References: <20230206-topic-sm8450-upstream-dp-controller-v6-0-d78313cbc41d@linaro.org> In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v6-0-d78313cbc41d@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio X-Mailer: b4 0.12.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the Display Port controller subnode to the MDSS node. Tested-by: Dmitry Baryshkov #SM8350-HDK Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 975ab4cbe57e..2618aaa6a9f2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2415,6 +2415,85 @@ dpu_intf2_out: endpoint { remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; + }; + }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; };