| Message ID | 20230214001906.1477370-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/xelpmp: Consider GSI offset when doing MCR lookups | expand |
> -----Original Message----- > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Matt > Roper > Sent: Monday, February 13, 2023 4:19 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org > Subject: [PATCH] drm/i915/xelpmp: Consider GSI offset when doing MCR > lookups > > MCR range tables use the final MMIO offset of a register (including the > 0x380000 GSI offset when applicable). Since the i915_mcr_reg_t passed > as a parameter during steering lookup does not include the GSI offset, > we need to add it back in for GSI registers before searching the tables. > > Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") LGTM, Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > index a4a8b8bc5737..03632df27de3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > @@ -561,12 +561,15 @@ static bool reg_needs_read_steering(struct intel_gt > *gt, > i915_mcr_reg_t reg, > enum intel_steering_type type) > { > - const u32 offset = i915_mmio_reg_offset(reg); > + u32 offset = i915_mmio_reg_offset(reg); > const struct intel_mmio_range *entry; > > if (likely(!gt->steering_table[type])) > return false; > > + if (IS_GSI_REG(offset)) > + offset += gt->uncore->gsi_offset; > + > for (entry = gt->steering_table[type]; entry->end; entry++) { > if (offset >= entry->start && offset <= entry->end) > return true; > -- > 2.39.1
On Wed, Feb 15, 2023 at 11:48:13AM -0800, Sripada, Radhakrishna wrote: > > > > -----Original Message----- > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Matt > > Roper > > Sent: Monday, February 13, 2023 4:19 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: dri-devel@lists.freedesktop.org > > Subject: [PATCH] drm/i915/xelpmp: Consider GSI offset when doing MCR > > lookups > > > > MCR range tables use the final MMIO offset of a register (including the > > 0x380000 GSI offset when applicable). Since the i915_mcr_reg_t passed > > as a parameter during steering lookup does not include the GSI offset, > > we need to add it back in for GSI registers before searching the tables. > > > > Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") > > LGTM, > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Thanks, applied to drm-intel-gt-next. Matt > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 5 ++++- > > 1 file changed, 4 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > index a4a8b8bc5737..03632df27de3 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c > > @@ -561,12 +561,15 @@ static bool reg_needs_read_steering(struct intel_gt > > *gt, > > i915_mcr_reg_t reg, > > enum intel_steering_type type) > > { > > - const u32 offset = i915_mmio_reg_offset(reg); > > + u32 offset = i915_mmio_reg_offset(reg); > > const struct intel_mmio_range *entry; > > > > if (likely(!gt->steering_table[type])) > > return false; > > > > + if (IS_GSI_REG(offset)) > > + offset += gt->uncore->gsi_offset; > > + > > for (entry = gt->steering_table[type]; entry->end; entry++) { > > if (offset >= entry->start && offset <= entry->end) > > return true; > > -- > > 2.39.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index a4a8b8bc5737..03632df27de3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -561,12 +561,15 @@ static bool reg_needs_read_steering(struct intel_gt *gt, i915_mcr_reg_t reg, enum intel_steering_type type) { - const u32 offset = i915_mmio_reg_offset(reg); + u32 offset = i915_mmio_reg_offset(reg); const struct intel_mmio_range *entry; if (likely(!gt->steering_table[type])) return false; + if (IS_GSI_REG(offset)) + offset += gt->uncore->gsi_offset; + for (entry = gt->steering_table[type]; entry->end; entry++) { if (offset >= entry->start && offset <= entry->end) return true;
MCR range tables use the final MMIO offset of a register (including the 0x380000 GSI offset when applicable). Since the i915_mcr_reg_t passed as a parameter during steering lookup does not include the GSI offset, we need to add it back in for GSI registers before searching the tables. Fixes: a7ec65fc7e83 ("drm/i915/xelpmp: Add multicast steering for media GT") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)