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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id x22-20020a1c7c16000000b003e8dc7a03basm2772434wmc.41.2023.03.09.06.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 06:23:09 -0800 (PST) From: Alexandre Mergnat Date: Thu, 09 Mar 2023 15:23:01 +0100 Subject: [PATCH 12/21] dt-bindings: pwm: add power-domains property MIME-Version: 1.0 Message-Id: <20230220-display-v1-12-45cbc68e188b@baylibre.com> References: <20230220-display-v1-0-45cbc68e188b@baylibre.com> In-Reply-To: <20230220-display-v1-0-45cbc68e188b@baylibre.com> To: =?unknown-8bit?b?RGFuaWVsIFZldHRlciA8ZGFuaWVsQGZmd2xsLmNoPiwgQ0sgSHUg?= =?unknown-8bit?b?PGNrLmh1QG1lZGlhdGVrLmNvbT4sIEppdGFvIFNoaSA8aml0YW8uc2hp?= =?unknown-8bit?b?QG1lZGlhdGVrLmNvbT4s?= =?unknown-8bit?q?_Thierry_Reding_=3Cthierry=2Ereding=40gmail=2Ecom=3E=2C_Phi?= =?unknown-8bit?q?lipp_Zabel_=3Cp=2Ezabel=40pengutronix=2Ede=3E=2C_Sam_Ravnb?= =?unknown-8bit?q?org_=3Csam=40ravnborg=2Eorg=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Uwe_Kleine-K?= =?unknown-8bit?q?=C3=B6nig_=3Cu=2Ekleine-koenig=40pengutronix=2Ede=3E=2C?= =?unknown-8bit?q?_Chun-Kuang_Hu_=3Cchunkuang=2Ehu=40kernel=2Eorg=3E=2C_Matth?= =?unknown-8bit?q?ias_Brugger_=3Cmatthias=2Ebgg=40gmail=2Ecom=3E=2C_David_Ai?= =?unknown-8bit?q?rlie_=3Cairlied=40gmail=2Ecom=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Xinlei_Lee_=3Cxinlei=2Elee=40mediatek=2Ecom?= =?unknown-8bit?q?=3E?= X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1514; i=amergnat@baylibre.com; h=from:subject:message-id; bh=kJNESBJYj6hSPaR8ChRMowMRY/WR5pgSKuWA0748F5c=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkCeu+nVEDPPb6Gdh+AgHCjdauH29RygOJmjr7a8NR ctAw6CiJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAnrvgAKCRArRkmdfjHURa2PD/ 9YzFDJCjDZcgP7CODOpyVYt/cRNXs9p9yTLCepRSRWMz1elUPgasCjdl78j9LEhjdZnZJ7+bWsn4sd 3pWRltutH9daZALNPyfqq2TuQqg2DxDkAhg25yaJg4DwtBIRfDCPbUYefAfg7dHVq/nQTgp+2Ugwf7 y7obSg5dgNYB+cP8n+8YVEIcW/X9+AzyMDSlM9VLOfhxGwuY1Qhw0Lb35fyj1BsQuIuJZMTVFXo+n4 z9G9Irii/MF2/kbweRjOX4bhoREmwPMBTa88ARJjWfafCOB0nN0g30wrvcGeaEoKHF58zv8slZkx8n Gyl5636sKO7qpvWuBsalHVEw9zOD3mrWD/B1Z+FlQ5VCpspfnMUP1jW22OUwTjDoam/z7yM3iBPrDN 7eghxhBtmd7N4z8jtmXJD1i+1Z4nwaLH6huBDUM7+2OlQzh7FvXQX3XKB5e640YK0GNoLlkBsvkcXD AX3xJvntzyAA4LpSDjGV5jQqE4NTbZQLAXOYQsACtSmX+Jbdp6OJPt2JPGj08J9OelBjwreAL88OV+ hyU5UJ7QxvojlmM/YmXvErdnrwpLlM3r7nCNFKwbRtF5LNgyJgu+QORw0+SJguftIAO1L150JGdBd7 0nLCkQfC7AGFO4tY/0f/dTUpmB8+P5wIZZpU9SrOuiqIk1Ld5leouoE5JK5w== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pwm@vger.kernel.org, Fabien Parent , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Guillaume La Roque , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to the Mediatek datasheet, the display PWM block has a power domain. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 0088bc8e7c54..8a0005a8bf40 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -51,6 +51,12 @@ properties: - const: main - const: mm + power-domains: + maxItems: 1 + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + required: - compatible - reg @@ -65,6 +71,7 @@ examples: #include #include #include + #include pwm0: pwm@1401e000 { compatible = "mediatek,mt8173-disp-pwm"; @@ -73,4 +80,5 @@ examples: clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; clock-names = "main", "mm"; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; };