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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id x22-20020a1c7c16000000b003e8dc7a03basm2772434wmc.41.2023.03.09.06.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 06:23:17 -0800 (PST) From: Alexandre Mergnat Date: Thu, 09 Mar 2023 15:23:07 +0100 Subject: [PATCH 18/21] drm/mediatek: dsi: Improves the DSI lane setup robustness MIME-Version: 1.0 Message-Id: <20230220-display-v1-18-45cbc68e188b@baylibre.com> References: <20230220-display-v1-0-45cbc68e188b@baylibre.com> In-Reply-To: <20230220-display-v1-0-45cbc68e188b@baylibre.com> To: =?unknown-8bit?b?RGFuaWVsIFZldHRlciA8ZGFuaWVsQGZmd2xsLmNoPiwgQ0sgSHUg?= =?unknown-8bit?b?PGNrLmh1QG1lZGlhdGVrLmNvbT4sIEppdGFvIFNoaSA8aml0YW8uc2hp?= =?unknown-8bit?b?QG1lZGlhdGVrLmNvbT4s?= =?unknown-8bit?q?_Thierry_Reding_=3Cthierry=2Ereding=40gmail=2Ecom=3E=2C_Phi?= =?unknown-8bit?q?lipp_Zabel_=3Cp=2Ezabel=40pengutronix=2Ede=3E=2C_Sam_Ravnb?= =?unknown-8bit?q?org_=3Csam=40ravnborg=2Eorg=3E=2C?= =?unknown-8bit?q?_Rob_Herring_=3Crobh+dt=40kernel=2Eorg=3E=2C_Uwe_Kleine-K?= =?unknown-8bit?q?=C3=B6nig_=3Cu=2Ekleine-koenig=40pengutronix=2Ede=3E=2C?= =?unknown-8bit?q?_Chun-Kuang_Hu_=3Cchunkuang=2Ehu=40kernel=2Eorg=3E=2C_Matth?= =?unknown-8bit?q?ias_Brugger_=3Cmatthias=2Ebgg=40gmail=2Ecom=3E=2C_David_Ai?= =?unknown-8bit?q?rlie_=3Cairlied=40gmail=2Ecom=3E=2C?= =?unknown-8bit?q?_Krzysztof_Kozlowski_=3Ckrzysztof=2Ekozlowski+dt=40linaro?= =?unknown-8bit?q?=2Eorg=3E=2C_Xinlei_Lee_=3Cxinlei=2Elee=40mediatek=2Ecom?= =?unknown-8bit?q?=3E?= X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1237; i=amergnat@baylibre.com; h=from:subject:message-id; bh=EBgpLyWateYNZX8XUe74shY32q1eVTHyK4Cgywlf4I4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkCeu+czZ0Nf/pPTdrIG0J4SybkuXb2pnV+MfQKa3s 6O0w84GJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAnrvgAKCRArRkmdfjHURRyID/ 9CnYh9rUbc4xP78TqMzB81pS2PcGxhOcRpKPDqDPBsQ8MkxsoG8+MY3aHW0oWOYwkkCKJILq1eWvrZ FcGBxafCafObuCEud3eX/BmgrilCpkw9k14ReSAhoLBleabN5e4BHhxGwdY4MppGPkp5z4tcO+cBKo 3NLvSlo7vGuU6t0pyo20+qO+Lgq7gyDW3qRYDQKyq8IaxIKxdTBJYJNUaZ7ys7TuQ4ljzSqdtle4xJ l2BNqkNuQfsq8NQ33JmFcv8fr8OjREJ1MkMJcGQ8yjmF7odFz0S00bNX8mOTCDNkuyL/gbUpMwym7j UDpymWJ38bRBsUoDiVbCZvFkpLyxmO9FD4OYNAK/FsSDWLAHsuSbWiEVSTIoUEpTz40K5hrN4MTVVX ZMY6bRv+KWIIfOqflp4HPRxHbMEPykdomliNR+UpGXU9RbGmiOVSIox47gyIK2ehXUPi6uR0hYmMA+ meTS4KhKpspzecO0R1jj2ocU73Bj8FMaBsR1ZeZQBxehsGGEyZnuPBeI87HC6zGceNO4bfmtxQMEoO qpVdgs/c2cZ3lBj7PKzAw29XuxFAzFRq6UIJPYku+GJtrC/ARlfmxQVgSbfP53xN+TxJ0znX0YGjAv qruUaP/4i4Vh0y3GHvZeBUTuyBur6wgU6j9w+hojKtE0FBIRpZOvzCRRta5w== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Neil Armstrong , Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pwm@vger.kernel.org, Fabien Parent , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Guillaume La Roque , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered before mtk_dsi_poweron. lanes_ready flag toggle to true during mtk_dsi_lane_ready function, and the DSI module is set up during mtk_dsi_poweron. Later, during panel driver init, mtk_dsi_lane_ready is triggered but does nothing because lanes are considered ready. Unfortunately, when the panel driver try to communicate, the DSI returns a timeout. The solution found here is to put lanes_ready flag to false after the DSI module setup into mtk_dsi_poweron to init the DSI lanes after the power / setup of the DSI module. Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 3b7d13028fb6..35c36cc05c04 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -667,6 +667,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + dsi->lanes_ready = false; + return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk);