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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id 27-20020a2e165b000000b002986a977bf2sm491529ljw.90.2023.03.14.08.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 08:28:48 -0700 (PDT) From: Konrad Dybcio Date: Tue, 14 Mar 2023 16:28:37 +0100 Subject: [PATCH v4 06/14] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v4-6-e987eb79d03f@linaro.org> References: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v4-0-e987eb79d03f@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678807716; l=1251; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SQf5xqv6dgkFv8lqaRaSsqR3oatLGI4JEKv+JlvqW4k=; b=j0wqavMQyp9JVzEUb+dyZ3aehx3l+F1HEWpU/j8PV1u7+qyWbwNnPl8Ix1vohsIlZY8QP7XOf0G8 gFxAnV4NCSDkUzx+xsz2mPlEqsuMhpdcxfpQLRfk7YgDSyVTBnNy X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is done in a6xx_bus_clear_pending_transactions(), but for the GMU-less ones we have to do it *somewhere*. Unhalting both side by side sounds like a good plan and it won't cause any issues if it's unnecessary. Also, add a memory barrier to ensure it's gone through. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a90847a3379a..70e9bd21ba3b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1015,8 +1015,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);