From patchwork Sat May 20 12:19:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13249207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7355EC7EE2E for ; Sat, 20 May 2023 12:20:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0E2C10E168; Sat, 20 May 2023 12:19:53 +0000 (UTC) Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E2F610E067 for ; Sat, 20 May 2023 12:19:51 +0000 (UTC) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f3a166f8e9so2250780e87.0 for ; Sat, 20 May 2023 05:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684585189; x=1687177189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rmQkm9eIpP4KwgdytmogY94a+6CcbBOn0isFTbbL77w=; b=GhljqGlQ9QrJYz01T97CgWhEuftE3BCFDJDfX8TOr0Uv/vrDwwoJqb/dKqtIiSQihy 0Up8USCanLryU+94kUSU7vvMIvjV2YL2czuJdiNg0eOiUvnBzPu4fHYDVzhcOp0PcrE0 5YrHorq91hnQE8hlZt1EBdxlxro9KhJOfk1rBmUrJrq6Jrrwyb4Q3eqEDMto1j/n58a/ s4My0zz7ngoMT6xnFRjocwmTGD0DT4G6gFcEAuAU7Bve06sjn8FzWQCrT5emDVb3bc8Y mZPzgEDHZl5SIDrmeb+NBK9gooBw/4udrf6Kg8z4t0sq7h2uOKKKSW26Ns8SE58mgxdD ATaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684585189; x=1687177189; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rmQkm9eIpP4KwgdytmogY94a+6CcbBOn0isFTbbL77w=; b=hkDrpn+UYNkWBp8+2pLAJmU5bvR5kbL69sVNFEIkR6xMnEh0RU7nol4jHCVOVy4D2N AIH9jOtpeBc+csHX0TguVYeoQaEFig8U+qV88Ejy5j8RCliT4yuTQFqELy5SdTmokw7p 03x+qR/lWj+beBG/uiroLUYWhYTcmCSFTFgssdux3f0pyxZW5+nYfn0OQWsXb4j8XyAC dtjaMsdghDekX+lunhXcOJvDPVJpAsh7RDa2oOWZ0vVijgszrkT6YvrBalLp1xQTNgyN ZupCQfkDIwg+I0bg0cLPd3L1cTz1A38lc55Vx8GOYk3DSCkO8AiK5gsKE9a8G/Sgt8LH GFkw== X-Gm-Message-State: AC+VfDyjm2b1TjH/PegvsnEj/V1Hl4hGQLO9apNQe10niB987z68p9Mk Lr088YUlP7GmRcAAVJ/WsaPmDw== X-Google-Smtp-Source: ACHHUZ5SMYtQfZSfOxdP+wpOVRJcr3gIYTgyH8YLTpTt7snj1X5zK2JPWv1wybnTZC2EWbGlj5mtHA== X-Received: by 2002:a19:ad02:0:b0:4f3:89e6:23c0 with SMTP id t2-20020a19ad02000000b004f389e623c0mr1959554lfc.31.1684585189530; Sat, 20 May 2023 05:19:49 -0700 (PDT) Received: from [192.168.1.101] (abxi58.neoplus.adsl.tpnet.pl. [83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:19:49 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:41 +0200 Subject: [PATCH v7 01/18] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v7-1-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=3340; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=tsvULNaXlyrWUrFums1fREzn1GspuB/dkdkyVKPR2+Q=; b=hR7lS9j6vc87ibCvNyBxqs7N/dQx3yhb9sIDnPNtz7efm6lV4/n3C7lWkHZk9yVlTHVZZ3nbu a0jmxVcYWhaA1kOIGODDbGjjjmV+Qym+7PsP4b0BrjjEQcJkr6RbRlR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Krzysztof Kozlowski , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks we'd normally assign to the GMU as if they were a part of the GMU, even though they are not". It's a (good) software representation of the GMU_CX and GMU_GX register spaces within the GPUSS that helps us programatically treat these de-facto GMU-less parts in a way that's very similar to their GMU-equipped cousins, massively saving up on code duplication. The "wrapper" register space was specifically designed to mimic the layout of a real GMU, though it rather obviously does not have the M3 core et al. GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be specified under the GPU node, just like their older cousins. Account for that. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 5dabe7b6794b..58ca8912a8c3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -36,10 +36,7 @@ properties: reg-names: minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + maxItems: 3 interrupts: maxItems: 1 @@ -157,16 +154,62 @@ allOf: required: - clocks - clock-names + - if: properties: compatible: contains: - pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' - - then: # Since Adreno 6xx series clocks should be defined in GMU + enum: + - qcom,adreno-610.0 + - qcom,adreno-619.1 + then: properties: - clocks: false - clock-names: false + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gmu + description: CX GMU clock + - const: xo + description: GPUCC clocksource clock + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_dbgc + + required: + - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$' + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - |