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[83.9.2.58]) by smtp.gmail.com with ESMTPSA id y6-20020ac24466000000b004f37bd02a89sm244766lfl.287.2023.05.20.05.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 20 May 2023 05:20:12 -0700 (PDT) From: Konrad Dybcio Date: Sat, 20 May 2023 14:19:56 +0200 Subject: [PATCH v7 16/18] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching MIME-Version: 1.0 Message-Id: <20230223-topic-gmuwrapper-v7-16-ecc7aab83556@linaro.org> References: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> In-Reply-To: <20230223-topic-gmuwrapper-v7-0-ecc7aab83556@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1684585186; l=4275; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BAw+AXulufdWfQ7Do/vFFCENVdfYOHXil2y3DfYll6U=; b=J0mstrrKtTwDSEIz6MWE9BIeXAQLaOvyBFv2ogrxa92yW44Ou+95DFxoBwuXYISKK+GyvjLE5 n3Bd7AqdH2iAbp9tqCqlYiEZ6yAOakkxa+iDiUgIMoyKW6orao4Fp27 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Before transitioning to using per-SoC and not per-Adreno speedbin fuse values (need another patchset to land elsewhere), a good improvement/stopgap solution is to use adreno_is_aXYZ macros in place of explicit revision matching. Do so to allow differentiating between A619 and A619_holi. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 +++++++++--------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 14 ++++++++++++-- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 99bb3d16657a..5ad19978390c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2167,23 +2167,23 @@ static u32 adreno_7c3_get_speed_bin(u32 fuse) return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) +static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) { u32 val = UINT_MAX; - if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) + if (adreno_is_a618(adreno_gpu)) val = a618_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev)) + else if (adreno_is_a619(adreno_gpu)) val = a619_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) + else if (adreno_is_7c3(adreno_gpu)) val = adreno_7c3_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + else if (adreno_is_a640(adreno_gpu)) val = a640_get_speed_bin(fuse); - else if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + else if (adreno_is_a650(adreno_gpu)) val = a650_get_speed_bin(fuse); if (val == UINT_MAX) { @@ -2196,7 +2196,7 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) return (1 << val); } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) +static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) { u32 supp_hw; u32 speedbin; @@ -2215,7 +2215,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) return ret; } - supp_hw = fuse_to_supp_hw(dev, rev, speedbin); + supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2334,7 +2334,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, config->rev); + ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 7a5d595d4b99..21513cec038f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -268,9 +268,9 @@ static inline int adreno_is_a630(struct adreno_gpu *gpu) return gpu->revn == 630; } -static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +static inline int adreno_is_a640(struct adreno_gpu *gpu) { - return (gpu->revn == 640) || (gpu->revn == 680); + return gpu->revn == 640; } static inline int adreno_is_a650(struct adreno_gpu *gpu) @@ -289,6 +289,11 @@ static inline int adreno_is_a660(struct adreno_gpu *gpu) return gpu->revn == 660; } +static inline int adreno_is_a680(struct adreno_gpu *gpu) +{ + return gpu->revn == 680; +} + /* check for a615, a616, a618, a619 or any derivatives */ static inline int adreno_is_a615_family(struct adreno_gpu *gpu) { @@ -306,6 +311,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu); } +static inline int adreno_is_a640_family(struct adreno_gpu *gpu) +{ + return adreno_is_a640(gpu) || adreno_is_a680(gpu); +} + u64 adreno_private_address_space_size(struct msm_gpu *gpu); int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, uint32_t param, uint64_t *value, uint32_t *len);