diff mbox series

[03/10] drm/i915/dsc: move DSC tables to DRM DSC helper

Message ID 20230228113342.2051425-4-dmitry.baryshkov@linaro.org (mailing list archive)
State New, archived
Headers show
Series drm/i915: move DSC RC tables to drm_dsc_helper.c | expand

Commit Message

Dmitry Baryshkov Feb. 28, 2023, 11:33 a.m. UTC 
This moves DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/display/drm_dsc_helper.c  | 364 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
 include/drm/display/drm_dsc_helper.h      |   1 +
 3 files changed, 372 insertions(+), 312 deletions(-)

Comments

kernel test robot Feb. 28, 2023, 2:49 p.m. UTC | #1 
Hi Dmitry,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next linus/master v6.2 next-20230228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base:   git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:    https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: ia64-allyesconfig (https://download.01.org/0day-ci/archive/20230228/202302282203.ghUPsryf-lkp@intel.com/config)
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
        git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/gpu/drm/display/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282203.ghUPsryf-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead


vim +635 drivers/gpu/drm/display/drm_dsc_helper.c

   627	
   628	/**
   629	 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
   630	 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
   631	 *
   632	 * @vdsc_cfg: DSC Configuration data partially filled by driver
   633	 */
   634	int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
 > 635	{
   636		const struct rc_parameters *rc_params;
   637		int i;
   638	
   639		/* fractional BPP is not supported */
   640		if (vdsc_cfg->bits_per_pixel & 0xf)
   641			return -EINVAL;
   642	
   643		rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
   644					  vdsc_cfg->bits_per_component);
   645		if (!rc_params)
   646			return -EINVAL;
   647	
   648		vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
   649		vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
   650		vdsc_cfg->initial_offset = rc_params->initial_offset;
   651		vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
   652		vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
   653		vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
   654		vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
   655	
   656		for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
   657			vdsc_cfg->rc_range_params[i].range_min_qp =
   658				rc_params->rc_range_params[i].range_min_qp;
   659			vdsc_cfg->rc_range_params[i].range_max_qp =
   660				rc_params->rc_range_params[i].range_max_qp;
   661			/*
   662			 * Range BPG Offset uses 2's complement and is only a 6 bits. So
   663			 * mask it to get only 6 bits.
   664			 */
   665			vdsc_cfg->rc_range_params[i].range_bpg_offset =
   666				rc_params->rc_range_params[i].range_bpg_offset &
   667				DSC_RANGE_BPG_OFFSET_MASK;
   668		}
   669	
   670		return 0;
   671	}
   672	EXPORT_SYMBOL(drm_dsc_setup_rc_params);
   673
kernel test robot Feb. 28, 2023, 3:10 p.m. UTC | #2 
Hi Dmitry,

I love your patch! Perhaps something to improve:

[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on drm-intel/for-linux-next drm-intel/for-linux-next-fixes drm/drm-next v6.2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
base:   git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:    https://lore.kernel.org/r/20230228113342.2051425-4-dmitry.baryshkov%40linaro.org
patch subject: [PATCH 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
config: x86_64-randconfig-a002-20230227 (https://download.01.org/0day-ci/archive/20230228/202302282241.qRMAjDx8-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Dmitry-Baryshkov/drm-i915-dsc-change-DSC-param-tables-to-follow-the-DSC-model/20230228-193505
        git checkout ee048cb6c2ec7f7f92bea6b72e8cd3ef9921993e
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/display/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202302282241.qRMAjDx8-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/display/drm_dsc_helper.c:635: warning: expecting prototype for drm_dsc_compute_rc_parameters(). Prototype was for drm_dsc_setup_rc_params() instead


vim +635 drivers/gpu/drm/display/drm_dsc_helper.c

   627	
   628	/**
   629	 * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
   630	 * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
   631	 *
   632	 * @vdsc_cfg: DSC Configuration data partially filled by driver
   633	 */
   634	int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
 > 635	{
   636		const struct rc_parameters *rc_params;
   637		int i;
   638	
   639		/* fractional BPP is not supported */
   640		if (vdsc_cfg->bits_per_pixel & 0xf)
   641			return -EINVAL;
   642	
   643		rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
   644					  vdsc_cfg->bits_per_component);
   645		if (!rc_params)
   646			return -EINVAL;
   647	
   648		vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
   649		vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
   650		vdsc_cfg->initial_offset = rc_params->initial_offset;
   651		vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
   652		vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
   653		vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
   654		vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
   655	
   656		for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
   657			vdsc_cfg->rc_range_params[i].range_min_qp =
   658				rc_params->rc_range_params[i].range_min_qp;
   659			vdsc_cfg->rc_range_params[i].range_max_qp =
   660				rc_params->rc_range_params[i].range_max_qp;
   661			/*
   662			 * Range BPG Offset uses 2's complement and is only a 6 bits. So
   663			 * mask it to get only 6 bits.
   664			 */
   665			vdsc_cfg->rc_range_params[i].range_bpg_offset =
   666				rc_params->rc_range_params[i].range_bpg_offset &
   667				DSC_RANGE_BPG_OFFSET_MASK;
   668		}
   669	
   670		return 0;
   671	}
   672	EXPORT_SYMBOL(drm_dsc_setup_rc_params);
   673
Jani Nikula Feb. 28, 2023, 4:11 p.m. UTC | #3 
On Tue, 28 Feb 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> This moves DSC RC tables to DRM DSC helper. No additional code changes
> and/or cleanups are a part of this commit, it will be cleaned up in the
> followup commits.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/gpu/drm/display/drm_dsc_helper.c  | 364 ++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
>  include/drm/display/drm_dsc_helper.h      |   1 +
>  3 files changed, 372 insertions(+), 312 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index ab8679c158b5..deaa84722bd4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -307,6 +307,370 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
>  }
>  EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
>  
> +enum ROW_INDEX_BPP {
> +	ROW_INDEX_6BPP = 0,
> +	ROW_INDEX_8BPP,
> +	ROW_INDEX_10BPP,
> +	ROW_INDEX_12BPP,
> +	ROW_INDEX_15BPP,
> +	MAX_ROW_INDEX
> +};
> +
> +enum COLUMN_INDEX_BPC {
> +	COLUMN_INDEX_8BPC = 0,
> +	COLUMN_INDEX_10BPC,
> +	COLUMN_INDEX_12BPC,
> +	COLUMN_INDEX_14BPC,
> +	COLUMN_INDEX_16BPC,
> +	MAX_COLUMN_INDEX
> +};
> +
> +struct rc_parameters {
> +	u16 initial_xmit_delay;
> +	u8 first_line_bpg_offset;
> +	u16 initial_offset;
> +	u8 flatness_min_qp;
> +	u8 flatness_max_qp;
> +	u8 rc_quant_incr_limit0;
> +	u8 rc_quant_incr_limit1;
> +	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
> +};
> +
> +/*
> + * Selected Rate Control Related Parameter Recommended Values
> + * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> + */
> +static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> +{
> +	/* 6BPP/8BPC */
> +	{ 768, 15, 6144, 3, 13, 11, 11, {
> +		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> +		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> +		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> +		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> +		}
> +	},
> +	/* 6BPP/10BPC */
> +	{ 768, 15, 6144, 7, 17, 15, 15, {
> +		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> +		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> +		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> +		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> +		{ 17, 18, -12 }
> +		}
> +	},
> +	/* 6BPP/12BPC */
> +	{ 768, 15, 6144, 11, 21, 19, 19, {
> +		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> +		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> +		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> +		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> +		{ 21, 22, -12 }
> +		}
> +	},
> +	/* 6BPP/14BPC */
> +	{ 768, 15, 6144, 15, 25, 23, 23, {
> +		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> +		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> +		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> +		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> +		{ 25, 26, -12 }
> +		}
> +	},
> +	/* 6BPP/16BPC */
> +	{ 768, 15, 6144, 19, 29, 27, 27, {
> +		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> +		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> +		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> +		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> +		{ 29, 30, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 8BPP/8BPC */
> +	{ 512, 12, 6144, 3, 12, 11, 11, {
> +		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> +		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> +		}
> +	},
> +	/* 8BPP/10BPC */
> +	{ 512, 12, 6144, 7, 16, 15, 15, {
> +		/*
> +		 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> +		 * VESA DSC 1.1 Table E-5 sets it to 4.
> +		 */
> +		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> +		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> +		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> +		}
> +	},
> +	/* 8BPP/12BPC */
> +	{ 512, 12, 6144, 11, 20, 19, 19, {
> +		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> +		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> +		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> +		{ 21, 23, -12 }
> +		}
> +	},
> +	/* 8BPP/14BPC */
> +	{ 512, 12, 6144, 15, 24, 23, 23, {
> +		{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> +		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> +		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> +		{ 24, 25, -12 }
> +		}
> +	},
> +	/* 8BPP/16BPC */
> +	{ 512, 12, 6144, 19, 28, 27, 27, {
> +		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> +		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> +		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> +		{ 28, 29, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 10BPP/8BPC */
> +	{ 410, 15, 5632, 3, 12, 11, 11, {
> +		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> +		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> +		}
> +	},
> +	/* 10BPP/10BPC */
> +	{ 410, 15, 5632, 7, 16, 15, 15, {
> +		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> +		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> +		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> +		}
> +	},
> +	/* 10BPP/12BPC */
> +	{ 410, 15, 5632, 11, 20, 19, 19, {
> +		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> +		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> +		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> +		{ 19, 20, -12 }
> +		}
> +	},
> +	/* 10BPP/14BPC */
> +	{ 410, 15, 5632, 15, 24, 23, 23, {
> +		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> +		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> +		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> +		{ 23, 24, -12 }
> +		}
> +	},
> +	/* 10BPP/16BPC */
> +	{ 410, 15, 5632, 19, 28, 27, 27, {
> +		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> +		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> +		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> +		{ 27, 28, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 12BPP/8BPC */
> +	{ 341, 15, 2048, 3, 12, 11, 11, {
> +		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> +		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> +		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> +		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> +		}
> +	},
> +	/* 12BPP/10BPC */
> +	{ 341, 15, 2048, 7, 16, 15, 15, {
> +		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> +		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> +		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> +		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> +		}
> +	},
> +	/* 12BPP/12BPC */
> +	{ 341, 15, 2048, 11, 20, 19, 19, {
> +		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> +		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> +		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> +		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> +		{ 21, 23, -12 }
> +		}
> +	},
> +	/* 12BPP/14BPC */
> +	{ 341, 15, 2048, 15, 24, 23, 23, {
> +		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> +		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> +		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> +		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> +		{ 22, 23, -12 }
> +		}
> +	},
> +	/* 12BPP/16BPC */
> +	{ 341, 15, 2048, 19, 28, 27, 27, {
> +		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> +		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> +		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> +		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> +		{ 26, 27, -12 }
> +		}
> +	},
> +},
> +{
> +	/* 15BPP/8BPC */
> +	{ 273, 15, 2048, 3, 12, 11, 11, {
> +		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> +		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> +		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> +		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> +		}
> +	},
> +	/* 15BPP/10BPC */
> +	{ 273, 15, 2048, 7, 16, 15, 15, {
> +		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> +		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> +		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> +		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> +		}
> +	},
> +	/* 15BPP/12BPC */
> +	{ 273, 15, 2048, 11, 20, 19, 19, {
> +		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> +		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> +		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> +		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> +		{ 16, 17, -12 }
> +		}
> +	},
> +	/* 15BPP/14BPC */
> +	{ 273, 15, 2048, 15, 24, 23, 23, {
> +		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> +		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> +		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> +		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> +		{ 20, 21, -12 }
> +		}
> +	},
> +	/* 15BPP/16BPC */
> +	{ 273, 15, 2048, 19, 28, 27, 27, {
> +		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> +		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> +		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> +		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> +		{ 24, 25, -12 }
> +		}
> +	}
> +}
> +};
> +
> +static int get_row_index_for_rc_params(u16 compressed_bpp)
> +{
> +	switch (compressed_bpp) {
> +	case 6:
> +		return ROW_INDEX_6BPP;
> +	case 8:
> +		return ROW_INDEX_8BPP;
> +	case 10:
> +		return ROW_INDEX_10BPP;
> +	case 12:
> +		return ROW_INDEX_12BPP;
> +	case 15:
> +		return ROW_INDEX_15BPP;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +static int get_column_index_for_rc_params(u8 bits_per_component)
> +{
> +	switch (bits_per_component) {
> +	case 8:
> +		return COLUMN_INDEX_8BPC;
> +	case 10:
> +		return COLUMN_INDEX_10BPC;
> +	case 12:
> +		return COLUMN_INDEX_12BPC;
> +	case 14:
> +		return COLUMN_INDEX_14BPC;
> +	case 16:
> +		return COLUMN_INDEX_16BPC;
> +	default:
> +		return -EINVAL;
> +	}
> +}
> +
> +static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> +						 u8 bits_per_component)
> +{
> +	int row_index, column_index;
> +
> +	row_index = get_row_index_for_rc_params(compressed_bpp);
> +	if (row_index < 0)
> +		return NULL;
> +
> +	column_index = get_column_index_for_rc_params(bits_per_component);
> +	if (column_index < 0)
> +		return NULL;
> +
> +	return &rc_parameters[row_index][column_index];
> +}
> +
> +/**
> + * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in

Copy-paste function name left in. ;)

> + * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
> + *
> + * @vdsc_cfg: DSC Configuration data partially filled by driver

Maybe mention what needs to be set beforehands? Or better yet, warn
about missing setup and return -EINVAL? *shrug*

Returns?

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> + */
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +{
> +	const struct rc_parameters *rc_params;
> +	int i;
> +
> +	/* fractional BPP is not supported */
> +	if (vdsc_cfg->bits_per_pixel & 0xf)
> +		return -EINVAL;
> +
> +	rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
> +				  vdsc_cfg->bits_per_component);
> +	if (!rc_params)
> +		return -EINVAL;
> +
> +	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> +	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> +	vdsc_cfg->initial_offset = rc_params->initial_offset;
> +	vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
> +	vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
> +	vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
> +	vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
> +
> +	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> +		vdsc_cfg->rc_range_params[i].range_min_qp =
> +			rc_params->rc_range_params[i].range_min_qp;
> +		vdsc_cfg->rc_range_params[i].range_max_qp =
> +			rc_params->rc_range_params[i].range_max_qp;
> +		/*
> +		 * Range BPG Offset uses 2's complement and is only a 6 bits. So
> +		 * mask it to get only 6 bits.
> +		 */
> +		vdsc_cfg->rc_range_params[i].range_bpg_offset =
> +			rc_params->rc_range_params[i].range_bpg_offset &
> +			DSC_RANGE_BPG_OFFSET_MASK;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(drm_dsc_setup_rc_params);
> +
>  /**
>   * drm_dsc_compute_rc_parameters() - Write rate control
>   * parameters to the dsc configuration defined in
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b4faab4c8fb3..d5a7e9494b23 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -18,24 +18,6 @@
>  #include "intel_qp_tables.h"
>  #include "intel_vdsc.h"
>  
> -enum ROW_INDEX_BPP {
> -	ROW_INDEX_6BPP = 0,
> -	ROW_INDEX_8BPP,
> -	ROW_INDEX_10BPP,
> -	ROW_INDEX_12BPP,
> -	ROW_INDEX_15BPP,
> -	MAX_ROW_INDEX
> -};
> -
> -enum COLUMN_INDEX_BPC {
> -	COLUMN_INDEX_8BPC = 0,
> -	COLUMN_INDEX_10BPC,
> -	COLUMN_INDEX_12BPC,
> -	COLUMN_INDEX_14BPC,
> -	COLUMN_INDEX_16BPC,
> -	MAX_COLUMN_INDEX
> -};
> -
>  struct rc_parameters {
>  	u16 initial_xmit_delay;
>  	u8 first_line_bpg_offset;
> @@ -47,296 +29,6 @@ struct rc_parameters {
>  	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
>  };
>  
> -/*
> - * Selected Rate Control Related Parameter Recommended Values
> - * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> - */
> -static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
> -{
> -	/* 6BPP/8BPC */
> -	{ 768, 15, 6144, 3, 13, 11, 11, {
> -		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
> -		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
> -		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
> -		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
> -		}
> -	},
> -	/* 6BPP/10BPC */
> -	{ 768, 15, 6144, 7, 17, 15, 15, {
> -		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
> -		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
> -		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
> -		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
> -		{ 17, 18, -12 }
> -		}
> -	},
> -	/* 6BPP/12BPC */
> -	{ 768, 15, 6144, 11, 21, 19, 19, {
> -		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
> -		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
> -		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
> -		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
> -		{ 21, 22, -12 }
> -		}
> -	},
> -	/* 6BPP/14BPC */
> -	{ 768, 15, 6144, 15, 25, 23, 23, {
> -		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
> -		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
> -		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
> -		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
> -		{ 25, 26, -12 }
> -		}
> -	},
> -	/* 6BPP/16BPC */
> -	{ 768, 15, 6144, 19, 29, 27, 27, {
> -		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
> -		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
> -		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
> -		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
> -		{ 29, 30, -12 }
> -		}
> -	},
> -},
> -{
> -	/* 8BPP/8BPC */
> -	{ 512, 12, 6144, 3, 12, 11, 11, {
> -		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> -		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> -		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> -		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> -		}
> -	},
> -	/* 8BPP/10BPC */
> -	{ 512, 12, 6144, 7, 16, 15, 15, {
> -		/*
> -		 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> -		 * VESA DSC 1.1 Table E-5 sets it to 4.
> -		 */
> -		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> -		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> -		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> -		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> -		}
> -	},
> -	/* 8BPP/12BPC */
> -	{ 512, 12, 6144, 11, 20, 19, 19, {
> -		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> -		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> -		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> -		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> -		{ 21, 23, -12 }
> -		}
> -	},
> -	/* 8BPP/14BPC */
> -	{ 512, 12, 6144, 15, 24, 23, 23, {
> -		{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
> -		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> -		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
> -		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
> -		{ 24, 25, -12 }
> -		}
> -	},
> -	/* 8BPP/16BPC */
> -	{ 512, 12, 6144, 19, 28, 27, 27, {
> -		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
> -		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> -		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
> -		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
> -		{ 28, 29, -12 }
> -		}
> -	},
> -},
> -{
> -	/* 10BPP/8BPC */
> -	{ 410, 15, 5632, 3, 12, 11, 11, {
> -		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
> -		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> -		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
> -		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
> -		}
> -	},
> -	/* 10BPP/10BPC */
> -	{ 410, 15, 5632, 7, 16, 15, 15, {
> -		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
> -		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> -		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
> -		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
> -		}
> -	},
> -	/* 10BPP/12BPC */
> -	{ 410, 15, 5632, 11, 20, 19, 19, {
> -		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
> -		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> -		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
> -		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
> -		{ 19, 20, -12 }
> -		}
> -	},
> -	/* 10BPP/14BPC */
> -	{ 410, 15, 5632, 15, 24, 23, 23, {
> -		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
> -		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> -		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
> -		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
> -		{ 23, 24, -12 }
> -		}
> -	},
> -	/* 10BPP/16BPC */
> -	{ 410, 15, 5632, 19, 28, 27, 27, {
> -		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
> -		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> -		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
> -		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
> -		{ 27, 28, -12 }
> -		}
> -	},
> -},
> -{
> -	/* 12BPP/8BPC */
> -	{ 341, 15, 2048, 3, 12, 11, 11, {
> -		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> -		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> -		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> -		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> -		}
> -	},
> -	/* 12BPP/10BPC */
> -	{ 341, 15, 2048, 7, 16, 15, 15, {
> -		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> -		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> -		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> -		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> -		}
> -	},
> -	/* 12BPP/12BPC */
> -	{ 341, 15, 2048, 11, 20, 19, 19, {
> -		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> -		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> -		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> -		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> -		{ 21, 23, -12 }
> -		}
> -	},
> -	/* 12BPP/14BPC */
> -	{ 341, 15, 2048, 15, 24, 23, 23, {
> -		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
> -		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
> -		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
> -		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
> -		{ 22, 23, -12 }
> -		}
> -	},
> -	/* 12BPP/16BPC */
> -	{ 341, 15, 2048, 19, 28, 27, 27, {
> -		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
> -		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
> -		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
> -		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
> -		{ 26, 27, -12 }
> -		}
> -	},
> -},
> -{
> -	/* 15BPP/8BPC */
> -	{ 273, 15, 2048, 3, 12, 11, 11, {
> -		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
> -		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
> -		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
> -		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
> -		}
> -	},
> -	/* 15BPP/10BPC */
> -	{ 273, 15, 2048, 7, 16, 15, 15, {
> -		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
> -		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
> -		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
> -		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
> -		}
> -	},
> -	/* 15BPP/12BPC */
> -	{ 273, 15, 2048, 11, 20, 19, 19, {
> -		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
> -		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
> -		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
> -		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
> -		{ 16, 17, -12 }
> -		}
> -	},
> -	/* 15BPP/14BPC */
> -	{ 273, 15, 2048, 15, 24, 23, 23, {
> -		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
> -		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
> -		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
> -		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
> -		{ 20, 21, -12 }
> -		}
> -	},
> -	/* 15BPP/16BPC */
> -	{ 273, 15, 2048, 19, 28, 27, 27, {
> -		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
> -		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
> -		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
> -		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
> -		{ 24, 25, -12 }
> -		}
> -	}
> -}
> -
> -};
> -
> -static int get_row_index_for_rc_params(u16 compressed_bpp)
> -{
> -	switch (compressed_bpp) {
> -	case 6:
> -		return ROW_INDEX_6BPP;
> -	case 8:
> -		return ROW_INDEX_8BPP;
> -	case 10:
> -		return ROW_INDEX_10BPP;
> -	case 12:
> -		return ROW_INDEX_12BPP;
> -	case 15:
> -		return ROW_INDEX_15BPP;
> -	default:
> -		return -EINVAL;
> -	}
> -}
> -
> -static int get_column_index_for_rc_params(u8 bits_per_component)
> -{
> -	switch (bits_per_component) {
> -	case 8:
> -		return COLUMN_INDEX_8BPC;
> -	case 10:
> -		return COLUMN_INDEX_10BPC;
> -	case 12:
> -		return COLUMN_INDEX_12BPC;
> -	case 14:
> -		return COLUMN_INDEX_14BPC;
> -	case 16:
> -		return COLUMN_INDEX_16BPC;
> -	default:
> -		return -EINVAL;
> -	}
> -}
> -
> -static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
> -						 u8 bits_per_component)
> -{
> -	int row_index, column_index;
> -
> -	row_index = get_row_index_for_rc_params(compressed_bpp);
> -	if (row_index < 0)
> -		return NULL;
> -
> -	column_index = get_column_index_for_rc_params(bits_per_component);
> -	if (column_index < 0)
> -		return NULL;
> -
> -	return &rc_parameters[row_index][column_index];
> -}
> -
>  bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
>  {
>  	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>  	const struct rc_parameters *rc_params;
>  	struct rc_parameters *rc = NULL;
>  	u8 i = 0;
> +	int ret;
>  
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
> @@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>  		calculate_rc_params(rc, vdsc_cfg);
>  		rc_params = rc;
>  	} else {
> -		rc_params = get_rc_params(compressed_bpp,
> -					  vdsc_cfg->bits_per_component);
> -		if (!rc_params)
> -			return -EINVAL;
> +		ret = drm_dsc_setup_rc_params(vdsc_cfg);
> +		if (ret)
> +			return ret;
> +
> +		goto out;
>  	}
>  
>  	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
> @@ -521,6 +215,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>  			vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
>  	}
>  
> +out:
>  	/*
>  	 * BitsPerComponent value determines mux_word_size:
>  	 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 706ba1d34742..1681791f65a5 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>  void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>  			      const struct drm_dsc_config *dsc_cfg);
>  void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
>  int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>  
>  #endif /* _DRM_DSC_HELPER_H_ */
diff mbox series

Patch

diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index ab8679c158b5..deaa84722bd4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -307,6 +307,370 @@  void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
 }
 EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
 
+enum ROW_INDEX_BPP {
+	ROW_INDEX_6BPP = 0,
+	ROW_INDEX_8BPP,
+	ROW_INDEX_10BPP,
+	ROW_INDEX_12BPP,
+	ROW_INDEX_15BPP,
+	MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+	COLUMN_INDEX_8BPC = 0,
+	COLUMN_INDEX_10BPC,
+	COLUMN_INDEX_12BPC,
+	COLUMN_INDEX_14BPC,
+	COLUMN_INDEX_16BPC,
+	MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+	u16 initial_xmit_delay;
+	u8 first_line_bpg_offset;
+	u16 initial_offset;
+	u8 flatness_min_qp;
+	u8 flatness_max_qp;
+	u8 rc_quant_incr_limit0;
+	u8 rc_quant_incr_limit1;
+	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+{
+	/* 6BPP/8BPC */
+	{ 768, 15, 6144, 3, 13, 11, 11, {
+		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+		}
+	},
+	/* 6BPP/10BPC */
+	{ 768, 15, 6144, 7, 17, 15, 15, {
+		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+		{ 17, 18, -12 }
+		}
+	},
+	/* 6BPP/12BPC */
+	{ 768, 15, 6144, 11, 21, 19, 19, {
+		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+		{ 21, 22, -12 }
+		}
+	},
+	/* 6BPP/14BPC */
+	{ 768, 15, 6144, 15, 25, 23, 23, {
+		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+		{ 25, 26, -12 }
+		}
+	},
+	/* 6BPP/16BPC */
+	{ 768, 15, 6144, 19, 29, 27, 27, {
+		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+		{ 29, 30, -12 }
+		}
+	},
+},
+{
+	/* 8BPP/8BPC */
+	{ 512, 12, 6144, 3, 12, 11, 11, {
+		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+		}
+	},
+	/* 8BPP/10BPC */
+	{ 512, 12, 6144, 7, 16, 15, 15, {
+		/*
+		 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+		 * VESA DSC 1.1 Table E-5 sets it to 4.
+		 */
+		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+		}
+	},
+	/* 8BPP/12BPC */
+	{ 512, 12, 6144, 11, 20, 19, 19, {
+		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+		{ 21, 23, -12 }
+		}
+	},
+	/* 8BPP/14BPC */
+	{ 512, 12, 6144, 15, 24, 23, 23, {
+		{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+		{ 24, 25, -12 }
+		}
+	},
+	/* 8BPP/16BPC */
+	{ 512, 12, 6144, 19, 28, 27, 27, {
+		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+		{ 28, 29, -12 }
+		}
+	},
+},
+{
+	/* 10BPP/8BPC */
+	{ 410, 15, 5632, 3, 12, 11, 11, {
+		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+		}
+	},
+	/* 10BPP/10BPC */
+	{ 410, 15, 5632, 7, 16, 15, 15, {
+		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+		}
+	},
+	/* 10BPP/12BPC */
+	{ 410, 15, 5632, 11, 20, 19, 19, {
+		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+		{ 19, 20, -12 }
+		}
+	},
+	/* 10BPP/14BPC */
+	{ 410, 15, 5632, 15, 24, 23, 23, {
+		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+		{ 23, 24, -12 }
+		}
+	},
+	/* 10BPP/16BPC */
+	{ 410, 15, 5632, 19, 28, 27, 27, {
+		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+		{ 27, 28, -12 }
+		}
+	},
+},
+{
+	/* 12BPP/8BPC */
+	{ 341, 15, 2048, 3, 12, 11, 11, {
+		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+		}
+	},
+	/* 12BPP/10BPC */
+	{ 341, 15, 2048, 7, 16, 15, 15, {
+		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+		}
+	},
+	/* 12BPP/12BPC */
+	{ 341, 15, 2048, 11, 20, 19, 19, {
+		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+		{ 21, 23, -12 }
+		}
+	},
+	/* 12BPP/14BPC */
+	{ 341, 15, 2048, 15, 24, 23, 23, {
+		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+		{ 22, 23, -12 }
+		}
+	},
+	/* 12BPP/16BPC */
+	{ 341, 15, 2048, 19, 28, 27, 27, {
+		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+		{ 26, 27, -12 }
+		}
+	},
+},
+{
+	/* 15BPP/8BPC */
+	{ 273, 15, 2048, 3, 12, 11, 11, {
+		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+		}
+	},
+	/* 15BPP/10BPC */
+	{ 273, 15, 2048, 7, 16, 15, 15, {
+		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+		}
+	},
+	/* 15BPP/12BPC */
+	{ 273, 15, 2048, 11, 20, 19, 19, {
+		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+		{ 16, 17, -12 }
+		}
+	},
+	/* 15BPP/14BPC */
+	{ 273, 15, 2048, 15, 24, 23, 23, {
+		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+		{ 20, 21, -12 }
+		}
+	},
+	/* 15BPP/16BPC */
+	{ 273, 15, 2048, 19, 28, 27, 27, {
+		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+		{ 24, 25, -12 }
+		}
+	}
+}
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+	switch (compressed_bpp) {
+	case 6:
+		return ROW_INDEX_6BPP;
+	case 8:
+		return ROW_INDEX_8BPP;
+	case 10:
+		return ROW_INDEX_10BPP;
+	case 12:
+		return ROW_INDEX_12BPP;
+	case 15:
+		return ROW_INDEX_15BPP;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+	switch (bits_per_component) {
+	case 8:
+		return COLUMN_INDEX_8BPC;
+	case 10:
+		return COLUMN_INDEX_10BPC;
+	case 12:
+		return COLUMN_INDEX_12BPC;
+	case 14:
+		return COLUMN_INDEX_14BPC;
+	case 16:
+		return COLUMN_INDEX_16BPC;
+	default:
+		return -EINVAL;
+	}
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+						 u8 bits_per_component)
+{
+	int row_index, column_index;
+
+	row_index = get_row_index_for_rc_params(compressed_bpp);
+	if (row_index < 0)
+		return NULL;
+
+	column_index = get_column_index_for_rc_params(bits_per_component);
+	if (column_index < 0)
+		return NULL;
+
+	return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_compute_rc_parameters() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+	const struct rc_parameters *rc_params;
+	int i;
+
+	/* fractional BPP is not supported */
+	if (vdsc_cfg->bits_per_pixel & 0xf)
+		return -EINVAL;
+
+	rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+				  vdsc_cfg->bits_per_component);
+	if (!rc_params)
+		return -EINVAL;
+
+	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+	vdsc_cfg->initial_offset = rc_params->initial_offset;
+	vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+	vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+	vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+	vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+		vdsc_cfg->rc_range_params[i].range_min_qp =
+			rc_params->rc_range_params[i].range_min_qp;
+		vdsc_cfg->rc_range_params[i].range_max_qp =
+			rc_params->rc_range_params[i].range_max_qp;
+		/*
+		 * Range BPG Offset uses 2's complement and is only a 6 bits. So
+		 * mask it to get only 6 bits.
+		 */
+		vdsc_cfg->rc_range_params[i].range_bpg_offset =
+			rc_params->rc_range_params[i].range_bpg_offset &
+			DSC_RANGE_BPG_OFFSET_MASK;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
 /**
  * drm_dsc_compute_rc_parameters() - Write rate control
  * parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b4faab4c8fb3..d5a7e9494b23 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@ 
 #include "intel_qp_tables.h"
 #include "intel_vdsc.h"
 
-enum ROW_INDEX_BPP {
-	ROW_INDEX_6BPP = 0,
-	ROW_INDEX_8BPP,
-	ROW_INDEX_10BPP,
-	ROW_INDEX_12BPP,
-	ROW_INDEX_15BPP,
-	MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
-	COLUMN_INDEX_8BPC = 0,
-	COLUMN_INDEX_10BPC,
-	COLUMN_INDEX_12BPC,
-	COLUMN_INDEX_14BPC,
-	COLUMN_INDEX_16BPC,
-	MAX_COLUMN_INDEX
-};
-
 struct rc_parameters {
 	u16 initial_xmit_delay;
 	u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@  struct rc_parameters {
 	struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
 };
 
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
-	/* 6BPP/8BPC */
-	{ 768, 15, 6144, 3, 13, 11, 11, {
-		{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
-		{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
-		{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
-		{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
-		}
-	},
-	/* 6BPP/10BPC */
-	{ 768, 15, 6144, 7, 17, 15, 15, {
-		{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
-		{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
-		{ 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
-		{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
-		{ 17, 18, -12 }
-		}
-	},
-	/* 6BPP/12BPC */
-	{ 768, 15, 6144, 11, 21, 19, 19, {
-		{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
-		{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
-		{ 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
-		{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
-		{ 21, 22, -12 }
-		}
-	},
-	/* 6BPP/14BPC */
-	{ 768, 15, 6144, 15, 25, 23, 23, {
-		{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
-		{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
-		{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
-		{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
-		{ 25, 26, -12 }
-		}
-	},
-	/* 6BPP/16BPC */
-	{ 768, 15, 6144, 19, 29, 27, 27, {
-		{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
-		{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
-		{ 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
-		{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
-		{ 29, 30, -12 }
-		}
-	},
-},
-{
-	/* 8BPP/8BPC */
-	{ 512, 12, 6144, 3, 12, 11, 11, {
-		{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
-		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
-		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
-		{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
-		}
-	},
-	/* 8BPP/10BPC */
-	{ 512, 12, 6144, 7, 16, 15, 15, {
-		/*
-		 * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
-		 * VESA DSC 1.1 Table E-5 sets it to 4.
-		 */
-		{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
-		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
-		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
-		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
-		}
-	},
-	/* 8BPP/12BPC */
-	{ 512, 12, 6144, 11, 20, 19, 19, {
-		{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
-		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
-		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
-		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
-		{ 21, 23, -12 }
-		}
-	},
-	/* 8BPP/14BPC */
-	{ 512, 12, 6144, 15, 24, 23, 23, {
-		{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
-		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
-		{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
-		{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
-		{ 24, 25, -12 }
-		}
-	},
-	/* 8BPP/16BPC */
-	{ 512, 12, 6144, 19, 28, 27, 27, {
-		{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
-		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
-		{ 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
-		{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
-		{ 28, 29, -12 }
-		}
-	},
-},
-{
-	/* 10BPP/8BPC */
-	{ 410, 15, 5632, 3, 12, 11, 11, {
-		{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
-		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
-		{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
-		{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
-		}
-	},
-	/* 10BPP/10BPC */
-	{ 410, 15, 5632, 7, 16, 15, 15, {
-		{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
-		{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
-		{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
-		{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
-		}
-	},
-	/* 10BPP/12BPC */
-	{ 410, 15, 5632, 11, 20, 19, 19, {
-		{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
-		{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
-		{ 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
-		{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
-		{ 19, 20, -12 }
-		}
-	},
-	/* 10BPP/14BPC */
-	{ 410, 15, 5632, 15, 24, 23, 23, {
-		{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
-		{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
-		{ 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
-		{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
-		{ 23, 24, -12 }
-		}
-	},
-	/* 10BPP/16BPC */
-	{ 410, 15, 5632, 19, 28, 27, 27, {
-		{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
-		{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
-		{ 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
-		{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
-		{ 27, 28, -12 }
-		}
-	},
-},
-{
-	/* 12BPP/8BPC */
-	{ 341, 15, 2048, 3, 12, 11, 11, {
-		{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
-		{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
-		{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
-		{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
-		}
-	},
-	/* 12BPP/10BPC */
-	{ 341, 15, 2048, 7, 16, 15, 15, {
-		{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
-		{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
-		{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
-		{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
-		}
-	},
-	/* 12BPP/12BPC */
-	{ 341, 15, 2048, 11, 20, 19, 19, {
-		{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
-		{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
-		{ 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
-		{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
-		{ 21, 23, -12 }
-		}
-	},
-	/* 12BPP/14BPC */
-	{ 341, 15, 2048, 15, 24, 23, 23, {
-		{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
-		{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
-		{ 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
-		{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
-		{ 22, 23, -12 }
-		}
-	},
-	/* 12BPP/16BPC */
-	{ 341, 15, 2048, 19, 28, 27, 27, {
-		{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
-		{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
-		{ 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
-		{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
-		{ 26, 27, -12 }
-		}
-	},
-},
-{
-	/* 15BPP/8BPC */
-	{ 273, 15, 2048, 3, 12, 11, 11, {
-		{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
-		{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
-		{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
-		{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
-		}
-	},
-	/* 15BPP/10BPC */
-	{ 273, 15, 2048, 7, 16, 15, 15, {
-		{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
-		{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
-		{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
-		{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
-		}
-	},
-	/* 15BPP/12BPC */
-	{ 273, 15, 2048, 11, 20, 19, 19, {
-		{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
-		{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
-		{ 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
-		{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
-		{ 16, 17, -12 }
-		}
-	},
-	/* 15BPP/14BPC */
-	{ 273, 15, 2048, 15, 24, 23, 23, {
-		{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
-		{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
-		{ 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
-		{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
-		{ 20, 21, -12 }
-		}
-	},
-	/* 15BPP/16BPC */
-	{ 273, 15, 2048, 19, 28, 27, 27, {
-		{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
-		{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
-		{ 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
-		{ 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
-		{ 24, 25, -12 }
-		}
-	}
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
-	switch (compressed_bpp) {
-	case 6:
-		return ROW_INDEX_6BPP;
-	case 8:
-		return ROW_INDEX_8BPP;
-	case 10:
-		return ROW_INDEX_10BPP;
-	case 12:
-		return ROW_INDEX_12BPP;
-	case 15:
-		return ROW_INDEX_15BPP;
-	default:
-		return -EINVAL;
-	}
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
-	switch (bits_per_component) {
-	case 8:
-		return COLUMN_INDEX_8BPC;
-	case 10:
-		return COLUMN_INDEX_10BPC;
-	case 12:
-		return COLUMN_INDEX_12BPC;
-	case 14:
-		return COLUMN_INDEX_14BPC;
-	case 16:
-		return COLUMN_INDEX_16BPC;
-	default:
-		return -EINVAL;
-	}
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
-						 u8 bits_per_component)
-{
-	int row_index, column_index;
-
-	row_index = get_row_index_for_rc_params(compressed_bpp);
-	if (row_index < 0)
-		return NULL;
-
-	column_index = get_column_index_for_rc_params(bits_per_component);
-	if (column_index < 0)
-		return NULL;
-
-	return &rc_parameters[row_index][column_index];
-}
-
 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
 {
 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	const struct rc_parameters *rc_params;
 	struct rc_parameters *rc = NULL;
 	u8 i = 0;
+	int ret;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 		calculate_rc_params(rc, vdsc_cfg);
 		rc_params = rc;
 	} else {
-		rc_params = get_rc_params(compressed_bpp,
-					  vdsc_cfg->bits_per_component);
-		if (!rc_params)
-			return -EINVAL;
+		ret = drm_dsc_setup_rc_params(vdsc_cfg);
+		if (ret)
+			return ret;
+
+		goto out;
 	}
 
 	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -521,6 +215,7 @@  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 			vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
 	}
 
+out:
 	/*
 	 * BitsPerComponent value determines mux_word_size:
 	 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@  int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
 			      const struct drm_dsc_config *dsc_cfg);
 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
 
 #endif /* _DRM_DSC_HELPER_H_ */