diff mbox series

[7/7] ARM: dts: qcom: msm8226: Add mdss nodes

Message ID 20230308-msm8226-mdp-v1-7-679f335d3d5b@z3ntu.xyz (mailing list archive)
State New, archived
Headers show
Series Display support for MSM8226 | expand

Commit Message

Luca Weiss May 29, 2023, 9:44 a.m. UTC
Add the nodes that describe the mdss so that display can work on
MSM8226.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++
 1 file changed, 118 insertions(+)

Comments

Konrad Dybcio May 29, 2023, 12:10 p.m. UTC | #1
On 29.05.2023 11:44, Luca Weiss wrote:
> Add the nodes that describe the mdss so that display can work on
> MSM8226.
> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>  arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 118 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
> index 42acb9ddb8cc..182d6405032f 100644
> --- a/arch/arm/boot/dts/qcom-msm8226.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -636,6 +636,124 @@ smd-edge {
>  				label = "lpass";
>  			};
>  		};
> +
> +		mdss: display-subsystem@fd900000 {
> +			compatible = "qcom,mdss";
> +			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
> +			reg-names = "mdss_phys", "vbif_phys";
> +
> +			power-domains = <&mmcc MDSS_GDSC>;
> +
> +			clocks = <&mmcc MDSS_AHB_CLK>,
> +				 <&mmcc MDSS_AXI_CLK>,
> +				 <&mmcc MDSS_VSYNC_CLK>;
> +			clock-names = "iface", "bus", "vsync";
One per line, please

> +
> +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
We're not using the irq cell, is that necessary/should that be 0?

> +
> +			status = "disabled";
status should go last

> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +
> +			mdp: display-controller@fd900000 {
> +				compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
> +				reg = <0xfd900100 0x22000>;
> +				reg-names = "mdp_phys";
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <0>;
> +
> +				clocks = <&mmcc MDSS_AHB_CLK>,
> +					 <&mmcc MDSS_AXI_CLK>,
> +					 <&mmcc MDSS_MDP_CLK>,
> +					 <&mmcc MDSS_VSYNC_CLK>;
> +				clock-names = "iface", "bus", "core", "vsync";
One per line, please

> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
Would port { work here? I remember one mdss component's bindings
didn't allow it but don't recall which one

> +
> +					port@0 {
> +						reg = <0>;
> +						mdp5_intf1_out: endpoint {
> +							remote-endpoint = <&dsi0_in>;
> +						};
> +					};
> +				};
> +			};
> +
> +			dsi0: dsi@fd922800 {
> +				compatible = "qcom,msm8226-dsi-ctrl",
> +					     "qcom,mdss-dsi-ctrl";
> +				reg = <0xfd922800 0x1f8>;
> +				reg-names = "dsi_ctrl";
> +
> +				interrupt-parent = <&mdss>;
> +				interrupts = <4>;
> +
> +				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
> +				assigned-clock-parents = <&dsi_phy0 0>, <&dsi_phy0 1>;
One per line, please

> +
> +				clocks = <&mmcc MDSS_MDP_CLK>,
> +					 <&mmcc MDSS_AHB_CLK>,
> +					 <&mmcc MDSS_AXI_CLK>,
> +					 <&mmcc MDSS_BYTE0_CLK>,
> +					 <&mmcc MDSS_PCLK0_CLK>,
> +					 <&mmcc MDSS_ESC0_CLK>,
> +					 <&mmcc MMSS_MISC_AHB_CLK>;
> +				clock-names = "mdp_core",
> +					      "iface",
> +					      "bus",
> +					      "byte",
> +					      "pixel",
> +					      "core",
> +					      "core_mmss";
> +
> +				phys = <&dsi_phy0>;
> +
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +						dsi0_in: endpoint {
> +							remote-endpoint = <&mdp5_intf1_out>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +						dsi0_out: endpoint {
> +						};
> +					};
> +				};
> +			};
> +
> +			dsi_phy0: phy@fd922a00 {
> +				compatible = "qcom,dsi-phy-28nm-8226";
> +				reg = <0xfd922a00 0xd4>,
> +				      <0xfd922b00 0x280>,
> +				      <0xfd922d80 0x30>;
> +				reg-names = "dsi_pll",
> +					    "dsi_phy",
> +					    "dsi_phy_regulator";
> +
> +				#clock-cells = <1>;
> +				#phy-cells = <0>;
> +
> +				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
One per line, please

Konrad
> +				clock-names = "iface", "ref";
> +			};
> +		};
>  	};
>  
>  	timer {
>
Dmitry Baryshkov May 29, 2023, 12:19 p.m. UTC | #2
On 29/05/2023 15:10, Konrad Dybcio wrote:
> 
> 
> On 29.05.2023 11:44, Luca Weiss wrote:
>> Add the nodes that describe the mdss so that display can work on
>> MSM8226.
>>
>> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
>> ---
>>   arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 118 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
>> index 42acb9ddb8cc..182d6405032f 100644
>> --- a/arch/arm/boot/dts/qcom-msm8226.dtsi
>> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
>> @@ -636,6 +636,124 @@ smd-edge {
>>   				label = "lpass";
>>   			};
>>   		};
>> +
>> +		mdss: display-subsystem@fd900000 {
>> +			compatible = "qcom,mdss";
>> +			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
>> +			reg-names = "mdss_phys", "vbif_phys";
>> +
>> +			power-domains = <&mmcc MDSS_GDSC>;
>> +
>> +			clocks = <&mmcc MDSS_AHB_CLK>,
>> +				 <&mmcc MDSS_AXI_CLK>,
>> +				 <&mmcc MDSS_VSYNC_CLK>;
>> +			clock-names = "iface", "bus", "vsync";
> One per line, please
> 
>> +
>> +			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			interrupt-controller;
>> +			#interrupt-cells = <1>;
> We're not using the irq cell, is that necessary/should that be 0?

No. With 0 it would mean that there is a single interrupt for mdss 
source, which clearly is not the case.

> 
>> +
>> +			status = "disabled";
> status should go last
> 
>> +
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +
>> +			mdp: display-controller@fd900000 {
>> +				compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
>> +				reg = <0xfd900100 0x22000>;
>> +				reg-names = "mdp_phys";
>> +
>> +				interrupt-parent = <&mdss>;
>> +				interrupts = <0>;
>> +
>> +				clocks = <&mmcc MDSS_AHB_CLK>,
>> +					 <&mmcc MDSS_AXI_CLK>,
>> +					 <&mmcc MDSS_MDP_CLK>,
>> +					 <&mmcc MDSS_VSYNC_CLK>;
>> +				clock-names = "iface", "bus", "core", "vsync";
> One per line, please
> 
>> +
>> +				ports {
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
> Would port { work here? I remember one mdss component's bindings
> didn't allow it but don't recall which one

Let's use ports /port@0 for uniformity even if there is just a single 
port always.

> 
>> +
>> +					port@0 {
>> +						reg = <0>;
>> +						mdp5_intf1_out: endpoint {
>> +							remote-endpoint = <&dsi0_in>;
>> +						};
>> +					};
>> +				};
>> +			};
>> +-- 
With best wishes
Dmitry
Konrad Dybcio May 29, 2023, 12:22 p.m. UTC | #3
On 29.05.2023 14:19, Dmitry Baryshkov wrote:
> On 29/05/2023 15:10, Konrad Dybcio wrote:
>>
>>
>> On 29.05.2023 11:44, Luca Weiss wrote:
>>> Add the nodes that describe the mdss so that display can work on
>>> MSM8226.
>>>
>>> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
>>> ---
>>>   arch/arm/boot/dts/qcom-msm8226.dtsi | 118 ++++++++++++++++++++++++++++++++++++
>>>   1 file changed, 118 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
>>> index 42acb9ddb8cc..182d6405032f 100644
>>> --- a/arch/arm/boot/dts/qcom-msm8226.dtsi
>>> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
>>> @@ -636,6 +636,124 @@ smd-edge {
>>>                   label = "lpass";
>>>               };
>>>           };
>>> +
>>> +        mdss: display-subsystem@fd900000 {
>>> +            compatible = "qcom,mdss";
>>> +            reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
>>> +            reg-names = "mdss_phys", "vbif_phys";
>>> +
>>> +            power-domains = <&mmcc MDSS_GDSC>;
>>> +
>>> +            clocks = <&mmcc MDSS_AHB_CLK>,
>>> +                 <&mmcc MDSS_AXI_CLK>,
>>> +                 <&mmcc MDSS_VSYNC_CLK>;
>>> +            clock-names = "iface", "bus", "vsync";
>> One per line, please
>>
>>> +
>>> +            interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <1>;
>> We're not using the irq cell, is that necessary/should that be 0?
> 
> No. With 0 it would mean that there is a single interrupt for mdss source, which clearly is not the case.
Obviously. Derp, sorry.

Konrad
> 
>>
>>> +
>>> +            status = "disabled";
>> status should go last
>>
>>> +
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +
>>> +            mdp: display-controller@fd900000 {
>>> +                compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
>>> +                reg = <0xfd900100 0x22000>;
>>> +                reg-names = "mdp_phys";
>>> +
>>> +                interrupt-parent = <&mdss>;
>>> +                interrupts = <0>;
>>> +
>>> +                clocks = <&mmcc MDSS_AHB_CLK>,
>>> +                     <&mmcc MDSS_AXI_CLK>,
>>> +                     <&mmcc MDSS_MDP_CLK>,
>>> +                     <&mmcc MDSS_VSYNC_CLK>;
>>> +                clock-names = "iface", "bus", "core", "vsync";
>> One per line, please
>>
>>> +
>>> +                ports {
>>> +                    #address-cells = <1>;
>>> +                    #size-cells = <0>;
>> Would port { work here? I remember one mdss component's bindings
>> didn't allow it but don't recall which one
> 
> Let's use ports /port@0 for uniformity even if there is just a single port always.
> 
>>
>>> +
>>> +                    port@0 {
>>> +                        reg = <0>;
>>> +                        mdp5_intf1_out: endpoint {
>>> +                            remote-endpoint = <&dsi0_in>;
>>> +                        };
>>> +                    };
>>> +                };
>>> +            };
>>> +-- 
> With best wishes
> Dmitry
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 42acb9ddb8cc..182d6405032f 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -636,6 +636,124 @@  smd-edge {
 				label = "lpass";
 			};
 		};
+
+		mdss: display-subsystem@fd900000 {
+			compatible = "qcom,mdss";
+			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
+			reg-names = "mdss_phys", "vbif_phys";
+
+			power-domains = <&mmcc MDSS_GDSC>;
+
+			clocks = <&mmcc MDSS_AHB_CLK>,
+				 <&mmcc MDSS_AXI_CLK>,
+				 <&mmcc MDSS_VSYNC_CLK>;
+			clock-names = "iface", "bus", "vsync";
+
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mdp: display-controller@fd900000 {
+				compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
+				reg = <0xfd900100 0x22000>;
+				reg-names = "mdp_phys";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_VSYNC_CLK>;
+				clock-names = "iface", "bus", "core", "vsync";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						mdp5_intf1_out: endpoint {
+							remote-endpoint = <&dsi0_in>;
+						};
+					};
+				};
+			};
+
+			dsi0: dsi@fd922800 {
+				compatible = "qcom,msm8226-dsi-ctrl",
+					     "qcom,mdss-dsi-ctrl";
+				reg = <0xfd922800 0x1f8>;
+				reg-names = "dsi_ctrl";
+
+				interrupt-parent = <&mdss>;
+				interrupts = <4>;
+
+				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
+				assigned-clock-parents = <&dsi_phy0 0>, <&dsi_phy0 1>;
+
+				clocks = <&mmcc MDSS_MDP_CLK>,
+					 <&mmcc MDSS_AHB_CLK>,
+					 <&mmcc MDSS_AXI_CLK>,
+					 <&mmcc MDSS_BYTE0_CLK>,
+					 <&mmcc MDSS_PCLK0_CLK>,
+					 <&mmcc MDSS_ESC0_CLK>,
+					 <&mmcc MMSS_MISC_AHB_CLK>;
+				clock-names = "mdp_core",
+					      "iface",
+					      "bus",
+					      "byte",
+					      "pixel",
+					      "core",
+					      "core_mmss";
+
+				phys = <&dsi_phy0>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						dsi0_in: endpoint {
+							remote-endpoint = <&mdp5_intf1_out>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+						dsi0_out: endpoint {
+						};
+					};
+				};
+			};
+
+			dsi_phy0: phy@fd922a00 {
+				compatible = "qcom,dsi-phy-28nm-8226";
+				reg = <0xfd922a00 0xd4>,
+				      <0xfd922b00 0x280>,
+				      <0xfd922d80 0x30>;
+				reg-names = "dsi_pll",
+					    "dsi_phy",
+					    "dsi_phy_regulator";
+
+				#clock-cells = <1>;
+				#phy-cells = <0>;
+
+				clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+				clock-names = "iface", "ref";
+			};
+		};
 	};
 
 	timer {