From patchwork Wed Mar 8 15:33:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13166004 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9418C6FD1E for ; Wed, 8 Mar 2023 15:34:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFEFB10E60C; Wed, 8 Mar 2023 15:34:25 +0000 (UTC) Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9E03D10E607 for ; Wed, 8 Mar 2023 15:34:19 +0000 (UTC) Received: by mail-qv1-xf31.google.com with SMTP id jo29so11355161qvb.0 for ; Wed, 08 Mar 2023 07:34:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1678289658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/cc1vOdWtwzxjB8Itoebo3PGpOUY7+SB1sP8jgG5BLo=; b=YoD4ttwbs43VKxfqZVBA8RXsYlw5CZm74f+e5Lh/kCbYdkWfNFqSGYc08xOUDBYk9P lZnvrLEzsfrbvfUiEhnaXnwkYHfR+CsmLGUeokIRahw+9k+tmcJ5xb3TyChoPVDo9/P1 l1VDO62R0d+LwA7NDoCm69wOXebeShbps3Yxk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678289658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/cc1vOdWtwzxjB8Itoebo3PGpOUY7+SB1sP8jgG5BLo=; b=AzmQiCjMe/FQbci1obsbe98mBr0V9ku60DfZi1Ao//lWOe6Fc3E1aiQ9H4Jf5RFLaJ atLNcTyepJcKYJZfbzLEvYQvGs1AhcUueDejIxzVjyOj+skw1KvoRUXotOmBge6FtNN1 uWLR3kpVyUB5+OdkpEOcrGuuMQgFqzq5b/zrkWFUAMOiqFfGH6FJKw5OhCVySs6rNP88 5v7mtqJbJPbLJZ4q2mACGZwZYgfzDoQ7tt+n/VoIxGGdmoenYST9fkKmtROUj83mqDug gEuodYalcyCSNJWI6PyqYG/7A9Y6rJeBOebsociWFgFo4pQFEtLKFS6ZBV9WdzcJXT59 PYtg== X-Gm-Message-State: AO0yUKVT2iH/WyRaQosIskpeC1TANImw3ATITED9SoHXe87vEvDp9CD8 MCrhg4bi/EzGG9p0vDmBqvkVYQ== X-Google-Smtp-Source: AK7set98642jUMtdHeymZDEKFYq0KpYGGdPN1pcP5RvZyBL1nfu9bZZzmMjm71u4d8JnE0Kaca57mg== X-Received: by 2002:ad4:5f4f:0:b0:56e:b59d:2ee7 with SMTP id p15-20020ad45f4f000000b0056eb59d2ee7mr35502459qvg.47.1678289658613; Wed, 08 Mar 2023 07:34:18 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:8752:d0ab:8bcc:f9a8]) by smtp.gmail.com with ESMTPSA id c134-20020ae9ed8c000000b0073d873df3fesm10506884qkg.30.2023.03.08.07.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 07:34:18 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 RESEND 2/3] drm/mediatek: Add support for AR30 and BA30 overlays Date: Wed, 8 Mar 2023 10:33:57 -0500 Message-Id: <20230308153358.333297-3-greenjustin@chromium.org> X-Mailer: git-send-email 2.40.0.rc0.216.gc4246ad0f0-goog In-Reply-To: <20230308153358.333297-1-greenjustin@chromium.org> References: <20230308153358.333297-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, greenjustin@chromium.org, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Tested using "modetest -P" on an MT8195 device. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8743c8047dc9..a6255e847104 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -89,6 +94,7 @@ struct mtk_disp_ovl_data { bool supports_afbc; const u32 *formats; size_t num_formats; + bool supports_clrfmt_ext; }; /* @@ -218,6 +224,30 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + if (!ovl->data->supports_clrfmt_ext) + return; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -332,9 +362,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -418,6 +450,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); }