From patchwork Thu Mar 9 21:04:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13168330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 051F2C74A5B for ; Thu, 9 Mar 2023 21:05:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 480D310E2BA; Thu, 9 Mar 2023 21:05:41 +0000 (UTC) Received: from mail-qt1-x82c.google.com (mail-qt1-x82c.google.com [IPv6:2607:f8b0:4864:20::82c]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E42D10E2B9 for ; Thu, 9 Mar 2023 21:05:33 +0000 (UTC) Received: by mail-qt1-x82c.google.com with SMTP id cf14so3555823qtb.10 for ; Thu, 09 Mar 2023 13:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1678395933; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=YPg0x50+7K+mExpb8ey1c0DmG8Z63jmrSKmXN9mbjNIdiSbYihqGEYA4DPpVC8+dgI x3txgSO6P6SXwZNS+NXfw/k60Re/13d2gYfhzdx7lBdcXx4QRAx5XqMmdtDZ7Y30sLw2 hlUo4KqC3DM5g1/7SG333WAip1KWx52SAco78= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678395933; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=xI0LMmMa+oSoHIqhrUdQDFNBfso7Ds6yyXqeo0LOZfiaIVQra1l5gGPii9cYZ0W2gp io3iZ9DfhOen9EPSu3ww4TuXFWaRhV/Wxgcjagr1mPvYqUTEKS8WCX+Ynrjrc0jmQlfE oYjo+KjFIULpiuxGLzk3Vn/+Xhe+DKm/hMYsbsKwA3INUt5noqvR3pUPf+FL5CAPshEx BDj7c5R6Hr72qz53iWiNGYyw2X6MCvEcsJmCR11Ylr4zBzsIepIEJoobFCYoO3LDTgQL U4nVX/5X0WK9ovmZpGi/fD+nMvFlx6OI7st4R9ChTqiIRIdvDEwgEBVJpqVg8QVhFiRP WVpQ== X-Gm-Message-State: AO0yUKUJy+7l/SwiCNbfDLVN1/elsK3vo4nHA70aRsj8G82WbQuAAbYg qiYsE1cR7LnNlAzmaRxZOn2OHQ== X-Google-Smtp-Source: AK7set/I4VnP5MmfF498RvMceJNf3jcWZbagRwc2tpTQtxdNF9CIfoTZfkmBdf6tHuD7VglGWsN7Jw== X-Received: by 2002:a05:622a:58e:b0:3b9:bf7f:66ff with SMTP id c14-20020a05622a058e00b003b9bf7f66ffmr37868701qtb.67.1678395932935; Thu, 09 Mar 2023 13:05:32 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:a575:2520:a8e1:989d]) by smtp.gmail.com with ESMTPSA id 69-20020a370548000000b007426f115a4esm14302375qkf.129.2023.03.09.13.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 13:05:32 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH v7 RESEND 2/3] drm/mediatek: Add support for AR30 and BA30 overlays Date: Thu, 9 Mar 2023 16:04:15 -0500 Message-Id: <20230309210416.1167020-3-greenjustin@chromium.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230309210416.1167020-1-greenjustin@chromium.org> References: <20230309210416.1167020-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, greenjustin@chromium.org, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the ability for the Mediatek DRM driver to control the bit depth register. If the DTS indicates the device supports 10-bit overlays and the current format has a fourcc of AR30, BA30, or RA30, we set the bit depth register to 10 bit. The next patch in the series actually enables 10-bit overlays for MT8195 devices, but this current patch should be a no-op. This patch was tested by simply running Chrome on an MT8195 and looking for regressions. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8743c8047dc9..a6255e847104 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -89,6 +94,7 @@ struct mtk_disp_ovl_data { bool supports_afbc; const u32 *formats; size_t num_formats; + bool supports_clrfmt_ext; }; /* @@ -218,6 +224,30 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + if (!ovl->data->supports_clrfmt_ext) + return; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -332,9 +362,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -418,6 +450,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); }