| Message ID | 20230405-add-dsc-support-v4-3-15daf84f8dcb@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC v1.2 Support for DSI | expand |
Can you fit DPU >= 7.0 in the title? On 2023-05-22 13:30:22, Jessica Zhang wrote: > Add DATA_COMPRESS feature flag to DPU INTF block. Nit: repeating the title, perhaps you can reflow this with the second paragraph? - Marijn > In DPU 7.x and later, DSC/DCE enablement registers have been moved from > PINGPONG to INTF. > > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > 2 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 7944481d0a33..8e12e07728df 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -104,7 +104,8 @@ > #define INTF_SC7180_MASK \ > (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) > > -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) > +#define INTF_SC7280_MASK \ > + (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)) > > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4eda2cc847ef..01c65f940f2a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -185,6 +185,7 @@ enum { > * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate > * than video timing > * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register > + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register > * @DPU_INTF_MAX > */ > enum { > @@ -192,6 +193,7 @@ enum { > DPU_INTF_TE, > DPU_DATA_HCTL_EN, > DPU_INTF_STATUS_SUPPORTED, > + DPU_INTF_DATA_COMPRESS, > DPU_INTF_MAX > }; > > > -- > 2.40.1 >
On 5/22/2023 1:47 PM, Marijn Suijten wrote: > Can you fit DPU >= 7.0 in the title? Hi Marijn, Sure. > > On 2023-05-22 13:30:22, Jessica Zhang wrote: >> Add DATA_COMPRESS feature flag to DPU INTF block. > > Nit: repeating the title, perhaps you can reflow this with the second > paragraph? Acked. Thanks, Jessica Zhang > > - Marijn > >> In DPU 7.x and later, DSC/DCE enablement registers have been moved from >> PINGPONG to INTF. >> >> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> >> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ >> 2 files changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 7944481d0a33..8e12e07728df 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -104,7 +104,8 @@ >> #define INTF_SC7180_MASK \ >> (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) >> >> -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) >> +#define INTF_SC7280_MASK \ >> + (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)) >> >> #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >> BIT(DPU_WB_UBWC) | \ >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index 4eda2cc847ef..01c65f940f2a 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -185,6 +185,7 @@ enum { >> * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate >> * than video timing >> * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register >> + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register >> * @DPU_INTF_MAX >> */ >> enum { >> @@ -192,6 +193,7 @@ enum { >> DPU_INTF_TE, >> DPU_DATA_HCTL_EN, >> DPU_INTF_STATUS_SUPPORTED, >> + DPU_INTF_DATA_COMPRESS, >> DPU_INTF_MAX >> }; >> >> >> -- >> 2.40.1 >>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 7944481d0a33..8e12e07728df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -104,7 +104,8 @@ #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) -#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) +#define INTF_SC7280_MASK \ + (INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) | BIT(DPU_INTF_DATA_COMPRESS)) #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 4eda2cc847ef..01c65f940f2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -185,6 +185,7 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register + * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -192,6 +193,7 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, + DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX };