diff mbox series

[v7,6/8] arm64: dts: renesas: r9a07g054: Add DU node

Message ID 20230411120810.368437-7-biju.das.jz@bp.renesas.com (mailing list archive)
State New, archived
Headers show
Series Add RZ/{G2L,G2LC} and RZ/V2L DU support | expand

Commit Message

Biju Das April 11, 2023, 12:08 p.m. UTC
Add DU node to RZ/V2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v7:
 * New patch.
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Geert Uytterhoeven April 20, 2023, 3:04 p.m. UTC | #1
Hi Biju,

On Tue, Apr 11, 2023 at 2:12 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add DU node to RZ/V2L SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v7:
>  * New patch.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> @@ -677,6 +677,20 @@ fcpvd: fcp@10880000 {
>                         resets = <&cpg R9A07G054_LCDC_RESET_N>;
>                 };
>
> +               du: display@10890000 {
> +                       compatible = "renesas,r9a07g054-du";

I think you have to make your mind up about using a fallback compatible
value or not. As the VSP has one, I think the DU should have one, too.

> +                       reg = <0 0x10890000 0 0x10000>;
> +                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
> +                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
> +                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
> +                       clock-names = "aclk", "pclk", "vclk";
> +                       power-domains = <&cpg>;
> +                       resets = <&cpg R9A07G054_LCDC_RESET_N>;
> +                       renesas,vsps = <&vspd 0>;
> +                       status = "disabled";
> +               };
> +
>                 cpg: clock-controller@11010000 {
>                         compatible = "renesas,r9a07g054-cpg";
>                         reg = <0 0x11010000 0 0x10000>;

Gr{oetje,eeting}s,

                        Geert
Biju Das April 20, 2023, 3:10 p.m. UTC | #2
Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v7 6/8] arm64: dts: renesas: r9a07g054: Add DU node
> 
> Hi Biju,
> 
> On Tue, Apr 11, 2023 at 2:12 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add DU node to RZ/V2L SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v7:
> >  * New patch.
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > @@ -677,6 +677,20 @@ fcpvd: fcp@10880000 {
> >                         resets = <&cpg R9A07G054_LCDC_RESET_N>;
> >                 };
> >
> > +               du: display@10890000 {
> > +                       compatible = "renesas,r9a07g054-du";
> 
> I think you have to make your mind up about using a fallback compatible
> value or not. As the VSP has one, I think the DU should have one, too.

Agreed.

Cheers,
Biju
> 
> > +                       reg = <0 0x10890000 0 0x10000>;
> > +                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
> > +                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
> > +                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
> > +                       clock-names = "aclk", "pclk", "vclk";
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg R9A07G054_LCDC_RESET_N>;
> > +                       renesas,vsps = <&vspd 0>;
> > +                       status = "disabled";
> > +               };
> > +
> >                 cpg: clock-controller@11010000 {
> >                         compatible = "renesas,r9a07g054-cpg";
> >                         reg = <0 0x11010000 0 0x10000>;
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 244934ce5991..c20bc859331d 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -677,6 +677,20 @@  fcpvd: fcp@10880000 {
 			resets = <&cpg R9A07G054_LCDC_RESET_N>;
 		};
 
+		du: display@10890000 {
+			compatible = "renesas,r9a07g054-du";
+			reg = <0 0x10890000 0 0x10000>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
+				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
+				 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
+			clock-names = "aclk", "pclk", "vclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A07G054_LCDC_RESET_N>;
+			renesas,vsps = <&vspd 0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a07g054-cpg";
 			reg = <0 0x11010000 0 0x10000>;