From patchwork Wed Apr 12 11:27:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13208936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39A36C77B7E for ; Wed, 12 Apr 2023 11:28:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4012F10E7B2; Wed, 12 Apr 2023 11:28:28 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87F6110E790 for ; Wed, 12 Apr 2023 11:28:10 +0000 (UTC) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 384476603268; Wed, 12 Apr 2023 12:28:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681298889; bh=BO9urXruQyNuXF4nM/TgzD/wYwtIsG4Yokws6tMujbw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SAt2DXz8F3hUnNbs1pp9rHQ81rEQD746/hrjZ+757Vgsd3quG/18wOKvcJh9CMrfR zFA0yyWVbUIv4aoYlO85o2PAfLDduFdgi0GiHUxAx3nT140GZszMd8nI22Yjcf7EnO iaOLVZWUhVcp30tMJjFUZ72anzKnBvKo+u2PUKZY3Dluhm89b0KJyswrxuT5V7uDV5 IJhdAZBDnQ1Htpq5HSVv5jJqxKmxoJn9TU3gHEwOM9lspc///2HsP/HVdI6a+MG0uH BfR86FPxhq8CW6ua4VFQV++ehaJlPnm14ijxwaH1Nivonbo1dYFCefonMilDODEcWK HobBtNylv+OZA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Subject: [PATCH 17/27] arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks Date: Wed, 12 Apr 2023 13:27:29 +0200 Message-Id: <20230412112739.160376-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230412112739.160376-1-angelogioacchino.delregno@collabora.com> References: <20230412112739.160376-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, thierry.reding@gmail.com, krzysztof.kozlowski+dt@linaro.org, linux-phy@lists.infradead.org, kernel@collabora.com, kishon@kernel.org, phone-devel@vger.kernel.org, jassisinghbrar@gmail.com, linux-pwm@vger.kernel.org, u.kleine-koenig@pengutronix.de, chunkuang.hu@kernel.org, jitao.shi@mediatek.com, xinlei.lee@mediatek.com, houlong.wei@mediatek.com, chunfeng.yun@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, vkoul@kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the MultiMedia System node, providing clocks for the multimedia hardware blocks and their IOMMU/SMIs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 99cc4918e6ba..a8b2c4517e79 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -635,6 +635,19 @@ mmc3: mmc@11260000 { status = "disabled"; }; + mmsys: syscon@14000000 { + compatible = "mediatek,mt6795-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; + assigned-clock-rates = <400000000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6795-vdecsys"; reg = <0 0x16000000 0 0x1000>;