From patchwork Wed Apr 12 11:27:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13208933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F086EC77B71 for ; Wed, 12 Apr 2023 11:28:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9695810E792; Wed, 12 Apr 2023 11:28:24 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id E5C1910E78D for ; Wed, 12 Apr 2023 11:28:11 +0000 (UTC) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 992EB660328C; Wed, 12 Apr 2023 12:28:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1681298890; bh=udYJL7+D0nU6SsvUw/ySN6/rdg1po5P1pPwUOP6NJ6Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MRVBOn4mP7A1tf5caIZVGKmwr24CaJNDm/AbiTnyf7L9hCauZ+fKHDnUCvpnlh2Gu hCLw6+5k9fn1t0edotlNf/dR1l6epND/bmS641hTNUfYEPSt2dgZoDLcmHxL1UE1Vr naKfvmShNyWBfXVB5qx2KZXnCOUqNcZ3VwTWYaSb8ig7dvXi/CBcw5HfmqJLg6HIWU qSFlSsB5xi4n+GdRG3N6WFbdYgA63kBtxZ85d5V97ynMiZ04EK2HkDhncPjrxM2gg9 GhM2i8GMulrF35oLSgxcJxz62pQNvA0zZ6uGfgbuyMBhw+06Eyiz3Q7lEQP+u1cQQt bjjb7seRYMYkg== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Subject: [PATCH 18/27] arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs Date: Wed, 12 Apr 2023 13:27:30 +0200 Message-Id: <20230412112739.160376-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230412112739.160376-1-angelogioacchino.delregno@collabora.com> References: <20230412112739.160376-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, thierry.reding@gmail.com, krzysztof.kozlowski+dt@linaro.org, linux-phy@lists.infradead.org, kernel@collabora.com, kishon@kernel.org, phone-devel@vger.kernel.org, jassisinghbrar@gmail.com, linux-pwm@vger.kernel.org, u.kleine-koenig@pengutronix.de, chunkuang.hu@kernel.org, jitao.shi@mediatek.com, xinlei.lee@mediatek.com, houlong.wei@mediatek.com, chunfeng.yun@mediatek.com, robh+dt@kernel.org, linux-mediatek@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, vkoul@kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add nodes for the multimedia IOMMU and its LARBs: this includes all but the MJC LARB, which cannot currently be used and will be added later. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index a8b2c4517e79..9cfa02085f61 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -390,6 +391,17 @@ systimer: timer@10200670 { clock-names = "clk13m"; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt6795-m4u"; + reg = <0 0x10205000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + #iommu-cells = <1>; + }; + apmixedsys: syscon@10209000 { compatible = "mediatek,mt6795-apmixedsys", "syscon"; reg = <0 0x10209000 0 0x1000>; @@ -648,16 +660,64 @@ mmsys: syscon@14000000 { mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + larb0: larb@14021000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x14021000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + }; + + smi_common: smi@14022000 { + compatible = "mediatek,mt6795-smi-common"; + reg = <0 0x14022000 0 0x1000>; + power-domains = <&spm MT6795_POWER_DOMAIN_MM>; + clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; + }; + vdecsys: clock-controller@16000000 { compatible = "mediatek,mt6795-vdecsys"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; + }; + vencsys: clock-controller@18000000 { compatible = "mediatek,mt6795-vencsys"; reg = <0 0x18000000 0 0x1000>; #clock-cells = <1>; }; + + larb3: larb@18001000 { + compatible = "mediatek,mt6795-smi-larb"; + reg = <0 0x18001000 0 0x1000>; + clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <3>; + power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; + }; }; };