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[83.9.31.242]) by smtp.gmail.com with ESMTPSA id d9-20020ac24c89000000b004f849605be7sm1774293lfl.292.2023.06.19.09.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 09:44:24 -0700 (PDT) From: Konrad Dybcio Date: Mon, 19 Jun 2023 18:44:21 +0200 Subject: [PATCH v3 1/6] drm/msm/a6xx: Add some missing header definitions MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v3-1-a3ce3725385b@linaro.org> References: <20230517-topic-a7xx_prep-v3-0-a3ce3725385b@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v3-0-a3ce3725385b@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687193061; l=862; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Kx6hGtFYbXC4+ZQmgSeqx9B48/cy4Oq5xhedcSdiIJ8=; b=OnXw3WN+NCUhzBUBk3dafn715zvedUkrCV0q0HBvZG8z537Nbfe7aX+wb40HJYP1gmD3mYT2h 74m/RiNDbQrCxoj1bxzaAKptoNt9xBoRY99JxQq6laKep3DHmP1LQPv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL bitfields. This may be substituted with a mesa header sync. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 9ab15d91aced..fcd9eb53baf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 +#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 + #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316