| Message ID | 20230517-topic-a7xx_prep-v3-4-a3ce3725385b@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Adreno QoL changes | expand |
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 5deb79924897..9929ff187368 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -790,6 +790,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, (1 << 31) | (0xa << 18) | (0xa0)); + /* + * Snapshots toggle the NMI bit which will result in a jump to the NMI + * handler instead of __main. Set the M3 config value to avoid that. + */ + gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); + chipid = adreno_gpu->rev.core << 24; chipid |= adreno_gpu->rev.major << 16; chipid |= adreno_gpu->rev.minor << 12;
While it's not very well understood, there is some sort of a fault handler implemented in the GMU firmware which triggers when a certain bit is set, resulting in the M3 core not booting up the way we expect it to. Write a magic value to a magic register to hopefully prevent that from happening. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++++++ 1 file changed, 6 insertions(+)