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[83.9.3.193]) by smtp.gmail.com with ESMTPSA id u26-20020a056512041a00b004f764716afdsm314395lfk.257.2023.06.20.04.10.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 04:10:41 -0700 (PDT) From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:36 +0200 Subject: [PATCH v4 1/6] drm/msm/a6xx: Add some missing header definitions MIME-Version: 1.0 Message-Id: <20230517-topic-a7xx_prep-v4-1-b16f273a91d4@linaro.org> References: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> In-Reply-To: <20230517-topic-a7xx_prep-v4-0-b16f273a91d4@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687259438; l=1618; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nFCkHKYu6fZpo1oSnNEiddoJoyEVOdH0h7thI2vrgRc=; b=nRNs41vgr+n4vunmbBJGhbFUhF0rOqAyzhYIrSjBneYnE0v0zDOxr59b2gyZGFeWygzWk4kvG lAeBkS8ItJnBMVlRG4ufwqSIzZt+uXkEJYGprGmhpUrCCrRH7krksb9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL bitfields. This may be substituted with a mesa header sync. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 4dc3be6ed45d..1c051535fd4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1166,6 +1166,9 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f +#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008 +#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 +#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 9ab15d91aced..fcd9eb53baf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 +#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 + #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316