From patchwork Fri May 26 03:05:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13256356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6083C7EE2E for ; Fri, 26 May 2023 03:06:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E989510E79B; Fri, 26 May 2023 03:06:40 +0000 (UTC) Received: from mail-io1-xd2d.google.com (mail-io1-xd2d.google.com [IPv6:2607:f8b0:4864:20::d2d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 80B6A10E798 for ; Fri, 26 May 2023 03:06:20 +0000 (UTC) Received: by mail-io1-xd2d.google.com with SMTP id ca18e2360f4ac-77489b6f68cso35754339f.1 for ; Thu, 25 May 2023 20:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685070379; x=1687662379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D2PG+QyRUP6Nq8VdIXvNjCkvOrIGM/v4hlMIxhvw9no=; b=K2yDLxw+/lRK+0F7kLjGq0RC5ZvkMPhZeblelYpVXyCkMiISxJe6agBzx2x/ZpZH/6 u/Unf2YlvqF6GVQ3kH8exB0l+3raeaoCxLvpFN82Gd7ddmYdrKFG7Hu0dYYa98L48cJq VOwC+dIMMGgK92w9tjWH4jCi41XksChlfGPEcJu85M+VujwD/VNSZ46xwMWt0jQuAuMI Jpo6JRLJxTlUA1HmQ9Ezox/uoluHpYOhSni+pESl2o2ap4Hx97p0wlOvmCHoYjNz8ck1 JaPGcA28bFJEZwlA8Oy+qcBk8PURnPhpVQ9YlL46hYnNaFy82J/EZj6AqSDXVZ1NDY7Z X2Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685070379; x=1687662379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D2PG+QyRUP6Nq8VdIXvNjCkvOrIGM/v4hlMIxhvw9no=; b=TxIq/vJ7b8JT1mtYF0IYkJ8FoK7WPcXczPzhYauZj3/PLge3pgC3S9uRNE8bgglqg3 yEf8tXASn2dcwOfnaz1FRR6t80FLEPziR01d5jhQq+4sYhECWxQFkXAuYNywSPEn/4fm CdDawZzyRajNERB9A5YsutQZWPh19fCwn/NPP1Y9BUjh8aFRqWaj65Z1nL+cPtQun1xi lNVTi9EMTDxtYJqehxCksIuU+knpSY0pLrSMUNZ/0DnmONTTfWkBh+3lodGyd2IhgFEl d1ryGr8wjdAZgSFODDnb3KBdRBQWqQ6oJdwWXgRAE+GlM59Y9o8YFFuYaIFzPiNlyTwD 1wwg== X-Gm-Message-State: AC+VfDwUyVylxlOqZZJexYwSCfjquIRxMxARAGlZr7h6GmimZVCL713B KmxpsnpkpZiVUuikQ2vMrmb3BxRuo68= X-Google-Smtp-Source: ACHHUZ7ginuUaWn/PgUoiQc+foiLRGBflvDWn0FZsE7YO26hUimQoMGVJYPUEly1URJhmisJNIvmIQ== X-Received: by 2002:a5d:9654:0:b0:769:8933:3c7f with SMTP id d20-20020a5d9654000000b0076989333c7fmr90624ios.9.1685070379084; Thu, 25 May 2023 20:06:19 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:3dd9:3f6c:9922:6420]) by smtp.gmail.com with ESMTPSA id i2-20020a5e8502000000b007702f55116fsm363189ioj.38.2023.05.25.20.06.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 20:06:18 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Subject: [PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode Date: Thu, 25 May 2023 22:05:58 -0500 Message-Id: <20230526030559.326566-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Neil Armstrong , Conor Dooley , Jernej Skrabec , Robert Foss , Krzysztof Kozlowski , Jonas Karlman , Laurent Pinchart , aford@beaconembedded.com, Frieder Schrempf , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Jagan Teki , Andrzej Hajda , Chen-Yu Tsai , Adam Ford , Marek Szyprowski Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 41f557fee29a..99ce2690582b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -667,11 +667,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m = &dsi->mode; + int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk = m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); - hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -943,7 +953,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz = dsi->hs_clock / 1000 / 8; int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1794,10 +1804,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) return PTR_ERR(pll_clk); } + /* If it doesn't exist, use pixel clock instead of failing */ ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate = 0; + } ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0);