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[83.9.3.193]) by smtp.gmail.com with ESMTPSA id 8-20020ac24828000000b004eed8de597csm335709lft.32.2023.06.20.04.30.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 04:30:04 -0700 (PDT) From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:29:59 +0200 Subject: [PATCH 2/2] drm/msm/dsi: Enable runtime PM MIME-Version: 1.0 Message-Id: <20230620-topic-dsiphy_rpm-v1-2-446a7fd0ce43@linaro.org> References: <20230620-topic-dsiphy_rpm-v1-0-446a7fd0ce43@linaro.org> In-Reply-To: <20230620-topic-dsiphy_rpm-v1-0-446a7fd0ce43@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687260601; l=898; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1cWWrhlZ0Hiex7ffMzQSl8xGBl+Dmf8ZnYPKI8QvzmU=; b=Rxf/R7lwV/VjnaZUBbyleX/36anDB/8YdzqjLCTn+vLf9T4VCV1JNySe1o/sOmyE/k4Ji5ClS YtUktVaBtcuDIdwFCQSc+bxJ+0LyhfAGpALqAfUulinnaE6EVrOs42Q X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , Marijn Suijten , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some devices power the DSI PHY/PLL through a power rail that we model as a GENPD. Enable runtime PM to make it suspendable. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 0a8e1dd4509e..323498237ef4 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -687,6 +687,10 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(phy->ahb_clk), "Unable to get ahb clk\n"); + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + /* PLL init will call into clk_register which requires * register access, so we need to enable power and ahb clock. */