| Message ID | 20230707183426.1952655-1-alan.previn.teres.alexis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/i915/pxp/mtl: Update gsc-heci cmd size and timeout | expand |
On Fri, 2023-07-07 at 11:34 -0700, Teres Alexis, Alan Previn wrote: > Update the max GSC-HECI packet size and the max firmware > response timeout to match internal fw specs. > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> I'm going to re-rev this and change the subject slightly to "Update gsc-heci cmd submission to align with spec". The two changes in this patch will be included but the cmd-packet size is now to be increased to 64K. Also, the counting of the timeout needs to start from when the request has his the cmd streamer hardware (not from when the PXP subsystem has thrown it over the wall to the GuC). Although this latter change would imply a longer timeout period, the change to observe this longer timeout should be applicable to code that is actually triggering a PXP session creation/teardown. In addition to that, we also need to update the LRC common defaults to inclure forcing the runalone bit for PXP contexts (as that is the updated hardware spec'd expectation). ...alan
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 0165d38fbead..c242b89ef31e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -15,7 +15,7 @@ #define PXP43_CMDID_INIT_SESSION 0x00000036 /* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K) +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K + SZ_4K) /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */ #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h index 298ad38e6c7d..a950d1e582d1 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h @@ -10,9 +10,9 @@ struct intel_pxp; -#define GSC_REPLY_LATENCY_MS 210 +#define GSC_REPLY_LATENCY_MS 360 /* - * Max FW response time is 200ms, to which we add 10ms to account for overhead + * Max FW response time is 350ms, to which we add 10ms to account for overhead * such as request preparation, GuC submission to hw and pipeline completion times. */ #define GSC_PENDING_RETRY_MAXCOUNT 40
Update the max GSC-HECI packet size and the max firmware response timeout to match internal fw specs. Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) base-commit: 8f40aae3b99ac28dd81d00933f5dc9124dbfc881