From patchwork Fri Jul 21 16:15:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13322244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32554EB64DD for ; Fri, 21 Jul 2023 16:16:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5023510E6CA; Fri, 21 Jul 2023 16:16:31 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 58EA210E6BF; Fri, 21 Jul 2023 16:16:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689956189; x=1721492189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BeVh0fq/BVRUQ2tN9OFik04ri1wMm/bj6fdQwBvOiV4=; b=DGfvsRAJh34tcgIji9HAGn0/Uduq0nBy7WwZEEkwjkb4kuRAnPykU+6i NrWW4BzSMSQ8gM1BSsn6inxazyt4UNy0oWhI0qFw6VJALVGzEm5gvb9HM PmUHxXkzFMDFUbRucUOSYfr1+g+Pq5oZZt1pLekBkZQ09OU7+YuAoD7Gt BbqVqwB1NWXcmw5hg+eKtcyCM/KqX2hLngA3iL8SjducWXJS4iWRiai20 q4+dSKg8OkZWHLwKHVyTnpEYq6YigmHq4Ynwj65JzjettBrn8oIdai9CL AcHS5ICMOAdzT9mFsAYpjltIQ8lkf7q8lDf70vgskQ2A9CGxbqUgbR+Jk g==; X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="433291954" X-IronPort-AV: E=Sophos;i="6.01,222,1684825200"; d="scan'208";a="433291954" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 09:15:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="675095403" X-IronPort-AV: E=Sophos;i="6.01,222,1684825200"; d="scan'208";a="675095403" Received: from hbockhor-mobl.ger.corp.intel.com (HELO intel.com) ([10.252.54.104]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 09:15:44 -0700 From: Andi Shyti To: Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das , Andrzej Hajda Subject: [PATCH v8 3/9] drm/i915/gt: Ensure memory quiesced before invalidation Date: Fri, 21 Jul 2023 18:15:08 +0200 Message-Id: <20230721161514.818895-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230721161514.818895-1-andi.shyti@linux.intel.com> References: <20230721161514.818895-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , linux-stable , dri-evel , Andi Shyti Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Jonathan Cavitt All memory traffic must be quiesced before requesting an aux invalidation on platforms that use Aux CCS. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Jonathan Cavitt Signed-off-by: Andi Shyti Cc: # v5.8+ Reviewed-by: Nirmoy Das Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 460c9225a50fc..6210b38a2d382 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -214,7 +214,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) { struct intel_engine_cs *engine = rq->engine; - if (mode & EMIT_FLUSH) { + /* + * On Aux CCS platforms the invalidation of the Aux + * table requires quiescing memory traffic beforehand + */ + if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) { u32 flags = 0; int err; u32 *cs;