From patchwork Thu Sep 21 14:15:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Andrzej Siewior X-Patchwork-Id: 13393956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E703FE7107D for ; Thu, 21 Sep 2023 14:15:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8749110E5B3; Thu, 21 Sep 2023 14:15:40 +0000 (UTC) Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by gabe.freedesktop.org (Postfix) with ESMTPS id 77D6A10E5B0 for ; Thu, 21 Sep 2023 14:15:27 +0000 (UTC) From: Sebastian Andrzej Siewior DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1695305726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nf89mi48+BTDl9P9LgC24tFBtIdB1s51h5vIjiQv4aM=; b=nfJnajQm2EfomGeimuqmYKDLizXeJivS+k4dgKb5mHbY+A2J42EWPVgFFt4MrmJVQhdT1T 01VAKFj7bsGz2SJfb+oeL1anUzjfdCM/NE8Aji8jXMlCfk2jwaynq5No7HC5Dham2aRIxi abZ3iQoR1W+TTxJ3I03KrTrSnWlirrjUY0cxjAByjybfYigGilZ31Jq3QOoxZ+WgUmIgGS iTQjyZSEr7vowPWotLkrxVbR4m3uouJObGYygKHeAhhTV5IjggswjqMh2wT0FYhkTLXUCY 4PtAdNzSkDmj1kC2Sns6pEv34qGcO4oVxDWt88MUXykKE5amRr+UZYyad+89Hg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1695305726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nf89mi48+BTDl9P9LgC24tFBtIdB1s51h5vIjiQv4aM=; b=vDdumqZ+OuhqqEqPf5tBX4Z38hg1tC9FoJ+b7EXxM+auQmdl0twrEvTK0dwjFvUhccxKDI j0SwiWJVTdARuDCw== To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH 4/5] drm/amd/display: Move the memory allocation out of dcn21_validate_bandwidth_fp(). Date: Thu, 21 Sep 2023 16:15:15 +0200 Message-Id: <20230921141516.520471-5-bigeasy@linutronix.de> In-Reply-To: <20230921141516.520471-1-bigeasy@linutronix.de> References: <20230921141516.520471-1-bigeasy@linutronix.de> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Sebastian Andrzej Siewior , "Pan, Xinhui" , Rodrigo Siqueira , Peter Zijlstra , Alex Deucher , Thomas Gleixner , =?utf-8?q?Christian_K=C3=B6nig?= Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" dcn21_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928 Signed-off-by: Sebastian Andrzej Siewior --- drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 10 +++++++++- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 7 ++----- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 5 ++--- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index d1a25fe6c44fa..5674c3450fc36 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -953,9 +953,17 @@ static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) { bool voltage_supported; + display_e2e_pipe_params_st *pipes; + + pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL); + if (!pipes) + return false; + DC_FP_START(); - voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate); + voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes); DC_FP_END(); + + kfree(pipes); return voltage_supported; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 5805fb02af14e..8b2038162a7e1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2216,9 +2216,8 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context, &context->bw_ctx.dml, pipes, pipe_cnt); } -bool dcn21_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate) +bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, + bool fast_validate, display_e2e_pipe_params_st *pipes) { bool out = false; @@ -2227,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); BW_VAL_TRACE_COUNT(); @@ -2267,7 +2265,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, out = false; validate_out: - kfree(pipes); BW_VAL_TRACE_FINISH(); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h index c51badf7b68a9..a81a0b9e68842 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h @@ -77,9 +77,8 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate); -bool dcn21_validate_bandwidth_fp(struct dc *dc, - struct dc_state *context, - bool fast_validate); +bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool + fast_validate, display_e2e_pipe_params_st *pipes); void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params); void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);