From patchwork Thu Oct 12 09:57:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 13418752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10BA4CDB46E for ; Thu, 12 Oct 2023 09:58:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8247910E484; Thu, 12 Oct 2023 09:57:53 +0000 (UTC) Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by gabe.freedesktop.org (Postfix) with ESMTPS id D446810E484 for ; Thu, 12 Oct 2023 09:57:50 +0000 (UTC) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E958B6607351; Thu, 12 Oct 2023 10:57:48 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104669; bh=s51bMlmGO1xHv5GaAY9hJMRyrYqHvYtjxvhr5nY4WEI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UMzZkGKNx/Iusi03ckaJHrfpWbCP71+BrRJ5QZQY9niamh66UrO9JhI0zRcAGwNKi NvJ6pexjpSYgCe5PGfja65/kjs0kEz/WSeGBjrHU4QEQXw9y8Bzo7kPl2+0s60upI3 HiiUSTxaMIFBVwemhn5359brPxiJxB4F4xdoxYgz0UpsDwH6ghSzIdXi5CRyzR9Jl4 GUk0TJHaqfCWWKZ0bNOdE+qq1jySMICiG9PXZWaaE0r+5xZqB9qFuuSlzH3JGnM7Bl X+HomRwIfu1vGD5CyPN+2SVzlTAqY0Sn61si+vrFBivsQPHMByEaTdniPGxST6drZG lCV4Cm8OjFp6A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Subject: [PATCH v11 07/16] drm/mediatek: aal: Use bitfield macros Date: Thu, 12 Oct 2023 11:57:27 +0200 Message-ID: <20231012095736.100784-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nfraprado@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, ehristev@collabora.com, wenst@chromium.org, matthias.bgg@gmail.com, kernel@collabora.com, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Reviewed-by: CK Hu Reviewed-by: Nícolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index dc26ddce0c6e..05f9be23fa47 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -18,6 +18,8 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 +#define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) +#define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 #define DISP_AAL_LUT_SIZE 512 @@ -51,9 +53,13 @@ void mtk_aal_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + u32 sz; - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); + sz = FIELD_PREP(DISP_AAL_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_AAL_SIZE_VSIZE, h); + + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } /**