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Thu, 23 May 2024 05:49:40 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 23 May 2024 14:49:24 +0200 Subject: [PATCH v4 11/15] drm/mediatek: dsi: Improves the DSI lane setup robustness MIME-Version: 1.0 Message-Id: <20231023-display-support-v4-11-ed82eb168fb1@baylibre.com> References: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> In-Reply-To: <20231023-display-support-v4-0-ed82eb168fb1@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1234; i=amergnat@baylibre.com; h=from:subject:message-id; bh=/0McRX6GoM2+nGIkWn2jaKs7S924L4q446vEYfmzgP4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBmTztTlpUBxrslkpM9KkVJFXYtjbSrCv5t3TWgUxI5 XUvLM5WJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZk87UwAKCRArRkmdfjHURWb4D/ 9wTBNeGwtAKm9fDQEgY3KlVoq3aw7N/I6ggPNiqm7lu48cT3alLmUEiAEH9cxr+ooYaOeF6xddtH9N Avqu+Na9+0o38iHIVyjOU/IB4Nrily2yDRjDJA1hvhAiygXW4A1rr7erHlTrJKuA6b2//3of5lwcpU C2WinPN+uvFvTf8s76ZBBRDLcMwz1YlFJDVcMZtHf9E+dCO1TDJ/LJ2LpyUQzYxDFC7dL9ClMU7bDh aRUcvXBSGYj02LWSk2KUBxbt8uL0pLsU5egoPTh0lwNl9Q/okAbJ31MY9AXCM02DXK/fha8WOx3xTw JhcIVPZo1pHFDMBCXeO00MmXu5eMyLfszMWYIpgAVBUZN7zkaJTlpoGza91wmPCNW7lZPpZLunm67n EjdgwfwctDV8gmmcaZagkU1NzGw/gQPe1/Nq6L/Xvp0LLsWKkYd7IlR/WS8XGhf3akmBJ+njq09a50 DygPcXf13zXLX9yQoQPT499tok9k750eiHUe7iwpZRUlxp//nSGY7rK7GyWBCNjVD488SyNYYHpOxd 3ZvRpJi4DnKnKauaFbFvyIFAJZDd7xzJn7haovlEAzvWt1bhVWvKVhImKpOcepGVrhBx73DT2+2SkV LVMKKq0yd/o08BjawyKMV9I+MVYefWOReRhG1sp/k3yb1r9aGKSO7tNJcPQQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered before mtk_dsi_poweron. lanes_ready flag toggle to true during mtk_dsi_lane_ready function, and the DSI module is set up during mtk_dsi_poweron. Later, during panel driver init, mtk_dsi_lane_ready is triggered but does nothing because lanes are considered ready. Unfortunately, when the panel driver try to communicate, the DSI returns a timeout. The solution found here is to put lanes_ready flag to false after the DSI module setup into mtk_dsi_poweron to init the DSI lanes after the power / setup of the DSI module. Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index e036d9394c23..cb546a9e9419 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -643,6 +643,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + dsi->lanes_ready = false; + return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk);