From patchwork Wed Jan 8 16:15:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13931271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13258E77188 for ; Wed, 8 Jan 2025 16:16:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91F7C10EBFB; Wed, 8 Jan 2025 16:16:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="BpZa8NYO"; dkim-atps=neutral Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by gabe.freedesktop.org (Postfix) with ESMTPS id E86CE10EBF6 for ; Wed, 8 Jan 2025 16:16:55 +0000 (UTC) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4363dc916ceso6934115e9.0 for ; Wed, 08 Jan 2025 08:16:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1736352954; x=1736957754; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wn0z/hnPHRXKbB0BiiICrVZl9kYhQ/tTXH5ga1zPWyc=; b=BpZa8NYO7tbzihc02nguunqbubDba+Nl1yw8H+avkBfU+ObEPbEzyS4hUDVTbupHyg MlXk3Y/djgt+m4Q1hSuUCj4J7lcqIitK5RbHFV3BNttkkvCG9xQhZ3cG9qlnzXW1PWid LvwtaXgYh+74p269WSkeKvh0iT5AZsyFyLGPyt4bXZdiMMEbOUxhuH2Rs41ms0aA7vDm LHplKO8xRoFiu5tPldq7aBGHeLy33xW68XLJnVFMfm475cWug31+3YjXpomjG0Mxpy0R 6D0Q48cmUONX3h1vPEZrAyzfVDSJ/O3nDKkXKxsNngpoY7FSWl3aU+SHcUwQgcHO8X1/ hIDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736352954; x=1736957754; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wn0z/hnPHRXKbB0BiiICrVZl9kYhQ/tTXH5ga1zPWyc=; b=TXzvoQElwvrHeI50nwZqHin8mV7tMgLoCZ3C4gxydybQIag19Re04OYzqG6AGsRuPw +2cxfsN1mwo2DYLQKgkXiiL8QjKgQmUk3GvBSbT7mEGC6Ndt4YtSA7JqwCuVIG1V05Ty WvqKkudEWWBqZkLPeV29f8JN4F8UDKu9TgxWXDAonySzzH5f16b1g+mUBcGyYw4tken3 l7Zv7ZpvzLMo6IaPwbyZQtHMWQGEFHod2JOBAuSjzdJpI01XsEHlNNCfGQCpejB8d4AA gcq1Yn661ArSG9+27w2tPuK2JqT7Wr9Ws9U8GpvLDqAO/sfs3S4LP62Epv3J0MdWLRtJ PPHA== X-Gm-Message-State: AOJu0Yz+a9tbS2ZrN8oRH1gM/RoLA5iyYate/1YHxjKrzbFVR1yuw0VU z84iSxhAb+QNDwggchhvgbaLJ+OuEY8puw8UJKD9+Lb7LPMvtvIuJyX9arjCKHI= X-Gm-Gg: ASbGncsp+PgpCT/vNlcCn3iKji7OA8eLahLXS+uI34Jda1xKenMfucrTTIz6cFI9tJE 8P3Nqc2bE7mlqrSaBfL1WwIjwZWY4+Xaa3ymtJdLO2B5/8ESXRlXraNLxu+Or9EgPqcPICiZJYm d8izKdJrjmfP4vMj4zfMkwWRtXUtehWk5jXCr7WtH2qvOLD+8eANm7yR+862bBJ4Za05t0Y9M8c a4fhphceHWXjaV3pbLzvF1vjDr3T0dreuCJmO0choUBJJM/cAnDstvSXp/j X-Google-Smtp-Source: AGHT+IHcsbLGPbCsRVGvojohrTvEnyypNhqIuN7WVwirYVpfixaNp8c/Hkxpo9jV/elwYELpq5m9lA== X-Received: by 2002:a05:600c:1d11:b0:434:e892:1033 with SMTP id 5b1f17b1804b1-436dc1b95ebmr61286195e9.2.1736352954396; Wed, 08 Jan 2025 08:15:54 -0800 (PST) Received: from [127.0.1.1] ([2a01:e0a:5ee:79d0:a6ac:e6d2:88e3:8ea1]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436dd14dfcasm44378105e9.1.2025.01.08.08.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2025 08:15:53 -0800 (PST) From: Alexandre Mergnat Date: Wed, 08 Jan 2025 17:15:48 +0100 Subject: [PATCH v5 6/7] arm64: dts: mediatek: add display blocks support for the MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v5-6-3905f1e4b835@baylibre.com> References: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> In-Reply-To: <20231023-display-support-v5-0-3905f1e4b835@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10846; i=amergnat@baylibre.com; h=from:subject:message-id; bh=yWk8HLzOpkZhXK2l7uxJYBkmU29C+tC9uY/Wa+pPUI8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBnfqSyzrt8ChVQ58c0u08e+XuEpdHbrq5PUizBV5YT N4r2AKqJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZ36ksgAKCRArRkmdfjHURZ2WD/ 0bs+zZU7Pak9RQ/RDLmf62ST/AUr1yNNRAzqybobUSZCl6seRBKUZRgV2RoHVEWdG5axUXT5aIMoIY DC7bvTKdypRLwTUpCXCAjPNg9dhDDe6CTicpsGia68igb5HT4dB1xTKVzU1GVDjKDLtRAvEnK5IT2l 3dSc+FnBui0xq2cRgFeAu9ITqy0T02j9Vnyojqx02F+JFDdrUrY8BAF8c9SuQjxboOPLPVPkbwzzKY dXAX0H+RNcz+r8wkLqJbqgBf1G47VzczvaQc6SQbaMewA9ovsQiUMycAPco4EiXdLs8F2v4V9ZaItk +2+SLacwGgKEV9+Tj3WbvEvCDLe3pWX+RsxotkZFcj1gBJq8O8TiMrYpXrOSYWWvRTmMWcB8SIf8pf EzH2/TDJpPyGI/JerWayYZmeMEFAW1rMsa5M3uiK2OMACpN1oEAVEJ1oYsbTxSNK2PecOrbE9V3K0x 3EFLfWF49POdn73Wmm1ueYhFrWAAN9mw60O4flQvEhiSQUfXILStzQFwGz09SkbukBnr0cny63KYak A+r3fYSqpZYTuPNHR1HxbKdgqcTIheb43e/jsbyYty6B7ip/RaZ2T0LBH2/idyzpo+hGzpvdfDWxjx P/NF1HYEEopTHiWQomgXxFgNGCM6sWHXbW3nunLX/9IcnCu2x9ynJD9NQtiQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 336 +++++++++++++++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 9c91fe8ea0f9..fdd570ca2d20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -19,6 +20,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -608,6 +622,15 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -704,6 +727,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -731,6 +763,26 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8365-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; smi_common: smi@14002000 { @@ -756,6 +808,290 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ovl0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ovl0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ccorr0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ccorr0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + aal0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + aal0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + gamma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + gamma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dither0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dither0_out: endpoint@0 { + reg = <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = ; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma1_out: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;