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Thu, 09 Jan 2025 02:38:04 -0800 (PST) Received: from [127.0.1.1] ([2a01:e0a:5ee:79d0:125:358f:ea05:210e]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-436e9dc8826sm16428195e9.11.2025.01.09.02.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jan 2025 02:38:04 -0800 (PST) From: Alexandre Mergnat Date: Thu, 09 Jan 2025 11:37:59 +0100 Subject: [PATCH v6 6/6] arm64: dts: mediatek: add display support for mt8365-evk MIME-Version: 1.0 Message-Id: <20231023-display-support-v6-6-c6af4f34f4d8@baylibre.com> References: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> In-Reply-To: <20231023-display-support-v6-0-c6af4f34f4d8@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , CK Hu , Catalin Marinas , Will Deacon , Simona Vetter , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7455; i=amergnat@baylibre.com; h=from:subject:message-id; bh=1m0qXFh3//q6MfFG9r23qNtH2/2eBC0zfGtjoyKtcMk=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBnf6cEDGICc17Hemx5nRkuZ9JxbBR8+kxV7ERRfeXo SRi3edaJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZ3+nBAAKCRArRkmdfjHURaaiEA DGgdGaSssQFlNm/QRhC+stujjMXix1zvGVcbmgJP0Vwm9BPsdMBhNnr4l2uoNjGKf+FBC9aewrOa8h LrsHrfLjCdDFtmOK7W4ANHtW9652n3BzzO4alc+uhp/JNVu+5eotfPePMi8Oa3cc7uaBVF1Mc6C4a1 gbA+GLyAknVaPnwAZpGqcY7NYJ2AFGWne4iYCPA1JmhOQ5mZSQyww9synvAEa/l5VsQ/A/IvOBqsR3 FO8ovLt8wfmZNSQiMUzSW2jxp2hy/k1GNnpaMYKgWqvwLn5+HQjQ0iFI4B0MaIeRe0ik1mLhBSx5kk FBMSQeehlbXSzKZRRF5Ri09F+BZQMuAXQDKhXCk0pnuiEqdp9wZY0Xmh3flV9egRPgLKipryhz7uvx 1ARDq+cUxJkh1XS5GF1jV96xxek6CxyzyKE8nQJGOj+WjwmdI2CfNmCVxsydMZp9Zw0GJOwB+DtvIt av0KV7oABDv4Lpic+8UCP53MC/tG7opgESt4tspppWll0bSayzdWAIECVTFbiuW6snezvGoXyY4flG YcWElOjaN3IOS/GkNWCDzMQ/exz7JWSgYUShwVfStbTQqDmRbw00ndOkyLLERAvhVeQxzGHxnpb+Zi lbVyY2iH+b069r+BIe6f41P6CSgrZD/QYiZLuhfks1GXH3NnJOKLqWtQFD1A== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 236 ++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 7d90112a7e27..70bd49a9d02f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -27,6 +27,21 @@ chosen { stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_connector_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -104,6 +119,16 @@ sound: sound { pinctrl-5 = <&aud_mosi_on_pins>; mediatek,platform = <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vsys_lcm"; + }; + }; &afe { @@ -131,6 +156,88 @@ &cpu3 { sram-supply = <&mt6357_vsram_proc_reg>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 = <&dpi_default_pins>; + pinctrl-1 = <&dpi_idle_pins>; + pinctrl-names = "default", "sleep"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dpi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dpi0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid015"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + #address-cells = <1>; + #size-cells = <0>; + panel_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dsi0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; @@ -161,6 +268,56 @@ &i2c0 { status = "okay"; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-div = <2>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + it66121_hdmi: hdmi@4c { + compatible = "ite,it66121"; + reg = <0x4c>; + #sound-dai-cells = <0>; + interrupt-parent = <&pio>; + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&ite_pins>; + pinctrl-names = "default"; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply = <&mt6357_vsim2_reg>; + vcn33-supply = <&mt6357_vibr_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + it66121_in: endpoint@0 { + reg = <0>; + bus-width = <12>; + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hdmi_connector_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -205,6 +362,11 @@ &mt6357_pmic { mediatek,micbias1-microvolt = <1700000>; }; +&mt6357_vsim1_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -267,6 +429,49 @@ clk-dat-pins { }; }; + dpi_default_pins: dpi-default-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux = ; @@ -308,6 +513,33 @@ pins { }; }; + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux = , + ; + output-high; + }; + + rst_ite_pins { + pinmux = ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux = ; @@ -463,6 +695,10 @@ &pwm { status = "okay"; }; +&rdma1_out { + remote-endpoint = <&dpi0_in>; +}; + &ssusb { dr_mode = "otg"; maximum-speed = "high-speed";