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(unknown [58.22.7.114]) by zwqz-smtp-mta-g5-3 (Coremail) with SMTP id _____wCnb01u+l1lDDPtDg--.50776S2; Wed, 22 Nov 2023 20:56:17 +0800 (CST) From: Andy Yan To: heiko@sntech.de Subject: [PATCH v2 12/12] arm64: dts: rockchip: Add vop on rk3588 Date: Wed, 22 Nov 2023 20:56:13 +0800 Message-Id: <20231122125613.3455091-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122125316.3454268-1-andyshrk@163.com> References: <20231122125316.3454268-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wCnb01u+l1lDDPtDg--.50776S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxAFWfAr4kKw17GFyfJF1UJrb_yoW5Zryxpa sruFWrJr4kuF1Iqan8KrWvgrWkAanYka1kKwn7CFy0yr1SvryDKFWfur1fJasrXr4xAanr tFsFyryUtrsxX3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jD-BNUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnBUwXlghlh8CIQAAs0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, s.hauer@pengutronix.de, chris.obbard@collabora.com, hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kever.yang@rock-chips.com, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, Andy Yan , sebastian.reichel@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Andy Yan Add vop dt node for rk3588. Signed-off-by: Andy Yan --- (no changes since v1) arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 7064c0e9179f..c1007b1cbead 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -362,6 +362,11 @@ spll: clock-0 { #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -474,6 +479,16 @@ sys_grf: syscon@fd58c000 { reg = <0x0 0xfd58c000 0x0 0x1000>; }; + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -593,6 +608,87 @@ i2c0: i2c@fd880000 { status = "disabled"; }; + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + resets = <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP0>, + <&cru SRST_D_VOP1>, + <&cru SRST_D_VOP2>, + <&cru SRST_D_VOP3>; + reset-names = "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + + status = "disabled"; + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>;