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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id e7-20020a056402104700b00542db304680sm5321002edu.63.2023.11.27.07.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:29:03 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:28:44 +0100 Subject: [PATCH v2 04/12] dt-bindings: firmware: qcom,scm: Allow interconnect for everyone MIME-Version: 1.0 Message-Id: <20231125-topic-rb1_feat-v2-4-979b28f35e4a@linaro.org> References: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> In-Reply-To: <20231125-topic-rb1_feat-v2-0-979b28f35e4a@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Will Deacon , Robin Murphy , Joerg Roedel , Krishna Manikandan , Robert Marko , Das Srinagesh , cros-qcom-dts-watchers@chromium.org X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701098925; l=1156; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ATWzTDawV1rfiW1Rmh2AEVyFtBtlEoO5VeMvQ1CdaLU=; b=d2uxm8koLiSmmdjKdjpShjLXryrZ+gjNkqEkIxKGxUdhaPhhQ69YN5mCvINv/crH2NFSPaxwY vbIbYzQoWl8CAPM339TI9Ayh67M741P51t4zrDzpIG103JKmvS20sDA X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Konrad Dybcio , iommu@lists.linux.dev, Marijn Suijten , freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Every Qualcomm SoC physically has a "CRYPTO0<->DDR" interconnect lane. Allow this property to be present, no matter the SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 0613a37a851a..f3a87a8426d0 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -178,21 +178,6 @@ allOf: minItems: 3 maxItems: 3 - # Interconnects - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,scm-qdu1000 - - qcom,scm-sc8280xp - - qcom,scm-sm8450 - - qcom,scm-sm8550 - then: - properties: - interconnects: false - # Interrupts - if: not: