diff mbox series

[v3,1/1] drm/i915/pxp: Add missing tag for Wa_14019159160

Message ID 20231127201150.8407-1-alan.previn.teres.alexis@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/1] drm/i915/pxp: Add missing tag for Wa_14019159160 | expand

Commit Message

Teres Alexis, Alan Previn Nov. 27, 2023, 8:11 p.m. UTC
Add missing tag for "Wa_14019159160 - Case 2" (for existing
PXP code that ensures run alone mode bit is set to allow
PxP-decryption.

 v3: - Check targeted platforms using IP_VAL. (John Harrison)
 v2: - Fix WA id number (John Harrison).
     - Improve comments and code to be specific
       for the targeted platforms (John Harrison)

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)


base-commit: 5429d55de723544dfc0630cf39d96392052b27a1

Comments

Matt Roper Nov. 28, 2023, 6:03 p.m. UTC | #1
On Mon, Nov 27, 2023 at 12:11:50PM -0800, Alan Previn wrote:
> Add missing tag for "Wa_14019159160 - Case 2" (for existing
> PXP code that ensures run alone mode bit is set to allow
> PxP-decryption.
> 
>  v3: - Check targeted platforms using IP_VAL. (John Harrison)
>  v2: - Fix WA id number (John Harrison).
>      - Improve comments and code to be specific
>        for the targeted platforms (John Harrison)
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7c367ba8d9dc..1152cf25d578 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -863,10 +863,12 @@ static bool ctx_needs_runalone(const struct intel_context *ce)
>  	bool ctx_is_protected = false;
>  
>  	/*
> -	 * On MTL and newer platforms, protected contexts require setting
> -	 * the LRC run-alone bit or else the encryption will not happen.
> +	 * Wa_14019159160 - Case 2: mtl
> +	 * On some platforms, protected contexts require setting
> +	 * the LRC run-alone bit or else the encryption/decryption will not happen.
> +	 * NOTE: Case 2 only applies to PXP use-case of said workaround.
>  	 */
> -	if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
> +	if (GRAPHICS_VER_FULL(ce->engine->i915) == IP_VER(12, 70) &&

The workaround database lists this as being needed on both 12.70 and
12.71.  Should this be a

        IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))

check instead?

The workaround is also listed in the database as applying to DG2; is
this "case 2" subset of the workaround not relevant to that platform?


Matt

>  	    (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {
>  		rcu_read_lock();
>  		gem_ctx = rcu_dereference(ce->gem_context);
> 
> base-commit: 5429d55de723544dfc0630cf39d96392052b27a1
> -- 
> 2.39.0
>
Teres Alexis, Alan Previn Nov. 29, 2023, 5:49 p.m. UTC | #2
On Tue, 2023-11-28 at 10:03 -0800, Roper, Matthew D wrote:
> On Mon, Nov 27, 2023 at 12:11:50PM -0800, Alan Previn wrote:
> > Add missing tag for "Wa_14019159160 - Case 2" (for existing
> > PXP code that ensures run alone mode bit is set to allow
> > PxP-decryption.
alan:snip.
alan: thanks for reviewing.
> > -	if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
> > +	if (GRAPHICS_VER_FULL(ce->engine->i915) == IP_VER(12, 70) &&
> 
> The workaround database lists this as being needed on both 12.70 and
> 12.71.  Should this be a
> 
>         IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))
alan: sure - will do this.
> 
> check instead?
> 
> The workaround is also listed in the database as applying to DG2; is
> this "case 2" subset of the workaround not relevant to that platform?
alan: i dont believe so - not the pxp case 2.
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 7c367ba8d9dc..1152cf25d578 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -863,10 +863,12 @@  static bool ctx_needs_runalone(const struct intel_context *ce)
 	bool ctx_is_protected = false;
 
 	/*
-	 * On MTL and newer platforms, protected contexts require setting
-	 * the LRC run-alone bit or else the encryption will not happen.
+	 * Wa_14019159160 - Case 2: mtl
+	 * On some platforms, protected contexts require setting
+	 * the LRC run-alone bit or else the encryption/decryption will not happen.
+	 * NOTE: Case 2 only applies to PXP use-case of said workaround.
 	 */
-	if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) &&
+	if (GRAPHICS_VER_FULL(ce->engine->i915) == IP_VER(12, 70) &&
 	    (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) {
 		rcu_read_lock();
 		gem_ctx = rcu_dereference(ce->gem_context);