From patchwork Wed Nov 29 22:02:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sui Jingfeng X-Patchwork-Id: 13473569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6DD8C4167B for ; Wed, 29 Nov 2023 22:02:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CBF7210E683; Wed, 29 Nov 2023 22:02:54 +0000 (UTC) Received: from out-172.mta0.migadu.com (out-172.mta0.migadu.com [91.218.175.172]) by gabe.freedesktop.org (Postfix) with ESMTPS id C008810E683 for ; Wed, 29 Nov 2023 22:02:51 +0000 (UTC) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1701295370; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=//reYtxdoo6wDb26q+jyDDkNTqsSVoXSTSF1yPvuPAA=; b=DfO6BD1cuI5HqEhZxyo4b/LKKaaPQJVJxC3hBnOrwPSyqs9oz6gucrMzZ8Fvb6H0k0QtFU 1I2D+yXRqa2YiS/seoQvogBtqcMW7OJUz2/BjVMqmy2fYva44e+PHjvCxyeSSoRjtXgAzH owLGeppviqeb+8BjAt+WHyU7qaKL+Sg= From: Sui Jingfeng To: Lucas Stach Subject: [etnaviv-next v12 5/8] drm/etnaviv: Add support for cached coherent caching mode Date: Thu, 30 Nov 2023 06:02:28 +0800 Message-Id: <20231129220231.12763-6-sui.jingfeng@linux.dev> In-Reply-To: <20231129220231.12763-1-sui.jingfeng@linux.dev> References: <20231129220231.12763-1-sui.jingfeng@linux.dev> MIME-Version: 1.0 X-Migadu-Flow: FLOW_OUT X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Gmeiner , Sui Jingfeng , etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Sui Jingfeng Modern Loongson CPUs choose to define the peripheral devices as DMA coherent by default, to be specific, the peripheral devices are capable of snooping CPU's cache. This means that device drivers do not need to manually maintain the coherency issue between a processor and an I/O for the cached mappings. Because such hardware features are host platform specific and vivante GPU IP has been integrated into different platform, probe the features before using is necessary. Therefore, Do the probe with the dev_is_dma_coherent() function and allow userspace to query. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 3 +++ drivers/gpu/drm/etnaviv/etnaviv_drv.h | 9 +++++++++ drivers/gpu/drm/etnaviv/etnaviv_gem.c | 16 ++++++++++++++-- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4 ++++ include/uapi/drm/etnaviv_drm.h | 1 + 5 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 8db86120b11d..883352aded32 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -66,6 +67,8 @@ static struct etnaviv_drm_private *etnaviv_alloc_private(struct device *dev) return ERR_PTR(-ENOMEM); } + priv->cached_coherent = dev_is_dma_coherent(dev); + return priv; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h index 9cd72948cfad..acc2e77ad2db 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h @@ -46,6 +46,15 @@ struct etnaviv_drm_private { struct xarray active_contexts; u32 next_context_id; + /* + * If true, the cached mapping is consistent for all CPU cores and + * bus masters(refer to GPU cores here) in the system. It means that + * both of the CPU and GPU will see the same data if the buffer being + * access is cached. And this coherency is guaranteed by host platform + * specific hardware, not maintained by software. + */ + bool cached_coherent; + /* list of GEM objects: */ struct mutex gem_lock; struct list_head gem_list; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index 71a6d2b1c80f..a72ca0a6883e 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -342,6 +342,7 @@ void *etnaviv_gem_vmap(struct drm_gem_object *obj) static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj) { struct page **pages; + pgprot_t prot; lockdep_assert_held(&obj->lock); @@ -349,8 +350,19 @@ static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj) if (IS_ERR(pages)) return NULL; - return vmap(pages, obj->base.size >> PAGE_SHIFT, - VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + switch (obj->flags) { + case ETNA_BO_CACHED: + prot = PAGE_KERNEL; + break; + case ETNA_BO_UNCACHED: + prot = pgprot_noncached(PAGE_KERNEL); + break; + case ETNA_BO_WC: + default: + prot = pgprot_writecombine(PAGE_KERNEL); + } + + return vmap(pages, obj->base.size >> PAGE_SHIFT, VM_MAP, prot); } static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 9db0fbfaf41a..c5a6d5809e2b 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -164,6 +164,10 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) *value = gpu->identity.eco_id; break; + case ETNAVIV_PARAM_CACHED_COHERENT: + *value = priv->cached_coherent; + break; + default: DBG("%s: invalid param: %u", dev_name(gpu->dev), param); return -EINVAL; diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h index af024d90453d..61eaa8cd0f5e 100644 --- a/include/uapi/drm/etnaviv_drm.h +++ b/include/uapi/drm/etnaviv_drm.h @@ -77,6 +77,7 @@ struct drm_etnaviv_timespec { #define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c #define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d #define ETNAVIV_PARAM_GPU_ECO_ID 0x1e +#define ETNAVIV_PARAM_CACHED_COHERENT 0x1f #define ETNA_MAX_PIPES 4