@@ -8,8 +8,8 @@ title: Rockchip SoC display controller (VOP2)
description:
VOP2 (Video Output Processor v2) is the display controller for the Rockchip
- series of SoCs which transfers the image data from a video memory
- buffer to an external LCD interface.
+ series of SoCs which transfers the image data from a video memory buffer to
+ an external LCD interface.
maintainers:
- Sandy Huang <hjc@rock-chips.com>
@@ -20,6 +20,7 @@ properties:
enum:
- rockchip,rk3566-vop
- rockchip,rk3568-vop
+ - rockchip,rk3588-vop
reg:
items:
@@ -27,8 +28,8 @@ properties:
Must contain one entry corresponding to the base address and length
of the register space.
- description:
- Can optionally contain a second entry corresponding to
- the CRTC gamma LUT address.
+ Can optionally contain a second entry corresponding to the CRTC gamma
+ LUT address.
reg-names:
items:
@@ -41,45 +42,63 @@ properties:
The VOP interrupt is shared by several interrupt sources, such as
frame start (VSYNC), line flag and other status interrupts.
+ # See compatible-specific constraints below.
clocks:
+ minItems: 5
items:
- - description: Clock for ddr buffer transfer.
- - description: Clock for the ahb bus to R/W the phy regs.
+ - description: Clock for ddr buffer transfer via axi.
+ - description: Clock for the ahb bus to R/W the regs.
- description: Pixel clock for video port 0.
- description: Pixel clock for video port 1.
- description: Pixel clock for video port 2.
+ - description: Pixel clock for video port 3.
+ - description: Peripheral(vop grf/dsi) clock.
clock-names:
+ minItems: 5
items:
- const: aclk
- const: hclk
- const: dclk_vp0
- const: dclk_vp1
- const: dclk_vp2
+ - const: dclk_vp3
+ - const: pclk_vop
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
- Phandle to GRF regs used for misc control
+ Phandle to GRF regs used for control the polarity of dclk/hsync/vsync of DPI,
+ also used for query vop memory bisr enable status, etc.
+
+ rockchip,vo1-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to VO GRF regs used for control the polarity of dclk/hsync/vsync of hdmi
+ on rk3588.
+
+ rockchip,vop-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to VOP GRF regs used for control data path between vopr and hdmi/edp.
+
+ rockchip,pmu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to PMU GRF used for query vop memory bisr status on rk3588.
ports:
$ref: /schemas/graph.yaml#/properties/ports
- properties:
- port@0:
+ patternProperties:
+ "^port@[0-3]$":
$ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP0
+ description: Output endpoint of VP0/1/2/3.
- port@1:
- $ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP1
+ required:
+ - port@0
- port@2:
- $ref: /schemas/graph.yaml#/properties/port
- description:
- Output endpoint of VP2
+ unevaluatedProperties: false
iommus:
maxItems: 1
@@ -96,6 +115,49 @@ required:
- clock-names
- ports
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3588-vop
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ clock-names:
+ minItems: 7
+
+ ports:
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+
+ required:
+ - rockchip,grf
+ - rockchip,vo1-grf
+ - rockchip,vop-grf
+ - rockchip,pmu
+
+ else:
+ properties:
+ rockchip,vo1-grf: false
+ rockchip,vop-grf: false
+ rockchip,pmu: false
+
+ clocks:
+ maxItems: 5
+ clock-names:
+ maxItems: 5
+
+ ports:
+ required:
+ - port@0
+ - port@1
+ - port@2
+
additionalProperties: false
examples: