From patchwork Fri Feb 16 14:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13560089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 71519C48BEF for ; Fri, 16 Feb 2024 14:25:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B81910E9E7; Fri, 16 Feb 2024 14:25:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="i6JHjH4x"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B23A10E9E7; Fri, 16 Feb 2024 14:25:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708093533; x=1739629533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HGi8+1GduWC+9MitmAaVSm2FEXLSDIcYUqS/naBxF1w=; b=i6JHjH4x7T7v+g9r3ptPqwRBmkT5kX9EdCS+7k+lla5FXPbdobkTWs7e 5O+zfuek3WJAh2tH+DuaBwtuS8kYK67jxcKa6FbJDikgd7OsocX17FaSK GOj25twkhhNZqxh27lKU/YA/HRk3vAVvg/mOJo8eeP9lErB8bH2VAfDN4 Der14B64CZWlzwGDu8ATmt+hFu6xjB8ottavA2DVR7EmxFtk5+/dcOcMW /xR1HDEx1+Wru9oIoQDdxEYhfHNhIGfRDpXH45UF9P4mvwwULTDb9Fp+e 0kg3+nNVxb30VSezFYgmaJ66bumW6wN6687CAOGQZjHjbu2i8l6kdsiiu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10985"; a="2372050" X-IronPort-AV: E=Sophos;i="6.06,164,1705392000"; d="scan'208";a="2372050" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2024 06:25:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,164,1705392000"; d="scan'208";a="34639158" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa002.jf.intel.com with ESMTP; 16 Feb 2024 06:25:31 -0800 From: Mitul Golani To: intel-gfx-trybot@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, dri-devel@lists.freedesktop.org, Mitul Golani Subject: [PATCH 4/6] drm/i915/display: Compute and Enable AS SDP Date: Fri, 16 Feb 2024 19:48:26 +0530 Message-Id: <20240216141828.1884193-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240216141828.1884193-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240216141828.1884193-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add necessary functions definitions to enable and compute AS SDP data. The new `intel_dp_compute_as_sdp` function computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR). --v2: - Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit] - separate patch for intel_read/write_dp_sdp [Ankit]. - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit] - To fix indentation [Ankit] --v3: - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. --v4: - Add HAS_VRR check before write as sdp. --v5: - Add missed HAS_VRR check before read as sdp. --v6: Use Adaptive Sync sink status, which can be used as a check for read/write sdp. (Ankit) Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d68fb9d45054..0759266e7bfb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2617,6 +2617,25 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; } +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; + struct intel_connector *connector = intel_dp->attached_connector; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int vrefresh = drm_mode_vrefresh(adjusted_mode); + + if (!intel_vrr_is_in_range(connector, vrefresh)) + return; + + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; + as_sdp->length = 0x9; + as_sdp->vtotal = adjusted_mode->vtotal; +} + static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -2942,6 +2961,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, g4x_dp_set_clock(encoder, pipe_config); intel_vrr_compute_config(pipe_config, conn_state); + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); intel_psr_compute_config(intel_dp, pipe_config, conn_state); intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);