| Message ID | 20240220211841.448846-20-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Add Display Port tunnel BW allocation support | expand |
> -----Original Message----- > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre > Deak > Sent: Wednesday, February 21, 2024 2:49 AM > To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org > Subject: [PATCH v2 19/21] drm/i915/dp: Suspend/resume DP tunnels > > Suspend and resume DP tunnels during system suspend/resume, disabling the BW > allocation mode during suspend, re-enabling it after resume. This reflects the > link's BW management component (Thunderbolt CM) disabling BWA during > suspend. Before any BW requests the driver must read the sink's DPRX > capabilities (since the BW manager requires this information, so snoops for it on > AUX), so ensure this read takes place. Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++++++----- > 1 file changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index a3dfcbb710027..35ef17439038a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -36,6 +36,7 @@ > #include <asm/byteorder.h> > > #include <drm/display/drm_dp_helper.h> > +#include <drm/display/drm_dp_tunnel.h> > #include <drm/display/drm_dsc_helper.h> #include > <drm/display/drm_hdmi_helper.h> #include <drm/drm_atomic_helper.h> @@ - > 3313,18 +3314,21 @@ void intel_dp_sync_state(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > - > - if (!crtc_state) > - return; > + bool dpcd_updated = false; > > /* > * Don't clobber DPCD if it's been already read out during output > * setup (eDP) or detect. > */ > - if (intel_dp->dpcd[DP_DPCD_REV] == 0) > + if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { > intel_dp_get_dpcd(intel_dp); > + dpcd_updated = true; > + } > > - intel_dp_reset_max_link_params(intel_dp); > + intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); > + > + if (crtc_state) > + intel_dp_reset_max_link_params(intel_dp); > } > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, @@ -5947,6 > +5951,8 @@ void intel_dp_encoder_suspend(struct intel_encoder > *intel_encoder) > struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); > > intel_pps_vdd_off_sync(intel_dp); > + > + intel_dp_tunnel_suspend(intel_dp); > } > > void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a3dfcbb710027..35ef17439038a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -36,6 +36,7 @@ #include <asm/byteorder.h> #include <drm/display/drm_dp_helper.h> +#include <drm/display/drm_dp_tunnel.h> #include <drm/display/drm_dsc_helper.h> #include <drm/display/drm_hdmi_helper.h> #include <drm/drm_atomic_helper.h> @@ -3313,18 +3314,21 @@ void intel_dp_sync_state(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - - if (!crtc_state) - return; + bool dpcd_updated = false; /* * Don't clobber DPCD if it's been already read out during output * setup (eDP) or detect. */ - if (intel_dp->dpcd[DP_DPCD_REV] == 0) + if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) { intel_dp_get_dpcd(intel_dp); + dpcd_updated = true; + } - intel_dp_reset_max_link_params(intel_dp); + intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); + + if (crtc_state) + intel_dp_reset_max_link_params(intel_dp); } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, @@ -5947,6 +5951,8 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); intel_pps_vdd_off_sync(intel_dp); + + intel_dp_tunnel_suspend(intel_dp); } void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
Suspend and resume DP tunnels during system suspend/resume, disabling the BW allocation mode during suspend, re-enabling it after resume. This reflects the link's BW management component (Thunderbolt CM) disabling BWA during suspend. Before any BW requests the driver must read the sink's DPRX capabilities (since the BW manager requires this information, so snoops for it on AUX), so ensure this read takes place. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)